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"Reference-less and Adaptive 2x Half-baud-rate Receivers"
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2023 International VLSI Symposium on Technology, Systems and Applications
³Ì¨Î½×¤å¼ú ®}·¸®¦¡§A 7~10.5-Gb/s Reference-Less Linear Half-rate CDR Circuit Using Automatic Band Selector¡¨
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2022 Synopsys·s«ä¬ì§Þ
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"Baud-Rate Clock/Data Recovery Circuits with Wide range FD and Jitter Tolerance Enhanced Technique"
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2021 VLSI-DAT
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2021«n¨È¬ì§Þ
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2020 VLSI-DAT
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2020Ápµú¬ì§Þ
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2019 IEEE ¥x¥_¤À·|
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2019Ápµú¬ì§Þ
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2018Ápµú¬ì§Þ
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"Design of 20Gbps Adaptive Linear Equalizer and Decision Feedback Equalizer"
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2017Ápµú¬ì§Þ
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Chih-Fan Liao and Shen-Iuan Liu, "A broadband noise-canceling CMOS LNA for 3.1-10.6-GHz UWB receivers", IEEE Journal of Solid-State Circuits, SC-42, pp. 329-339, Feb. 2007.
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[IEEE Solid-State Circuits Magazine, Fall 2016, p. 31]
Top-Cited IEEE Journal of Solid-State Circuits Papers
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2017©ô§»ª÷ª¿¼ú
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2017 IC³]pÄvÁÉ
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2016©ô§»ª÷ª¿¼ú
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ISSCC 2016
Che-Wei Yeh, Cheng-En Hsieh, and Shen-Iuan Liu, "A 3.2GHz digital phase-locked loop with background supply noise cancellation",
accepted by International Solid-State Circuits Conference (ISSCC) 2016.
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CIC 2015
Àuµ¥³]p¼ú  ÁÂ¥¿®¦ "§C¹qÀ£³v¦¸¹Gªñ¦¡Ãþ¤ñ¼Æ¦ìÂà´«¾¹³]p"
"A low-voltage SAR ADC design"
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