Date |
Lecture |
Lab |
Assignment |
Project |
09/17/2010 |
Overview (syllabus;
announce;
intro) |
Linux; X-editor (lab0) |
--- |
--- |
09/24/2010 |
Verilog (1): Cadence Verilog Language
- Chapter 1-11 |
Verilog Lab 1 (lab1) |
Verilog HW 1 (hw1)
due on 10/8; see announcements for submission |
--- |
10/01/2010 |
Verilog (2): Cadence Verilog Language - Chapter 11-17 |
Verilog Lab 2 (lab2) |
--- |
--- |
10/08/2010 |
Verilog (3): Behavior Modeling and
Debugging (LN3-1;
LN3-2) |
--- |
Verilog HW 2 (hw2)
due on 10/22; see announcements for submission |
--- |
10/15/2010 |
Verilog (4): Testbench Writing and
Synthesizable Codes (LN4-1;
LN4-2;
LN4-3;
LN4-4 for
self-study) |
--- |
--- |
Topics
Announced (pdf) |
10/22/2010 |
Synthesis (1): Design Compiler (LN5-1;
LN5-2) |
--- |
Verilog HW 3 (hw3)
due on 11/14 (extended) |
--- |
10/29/2010 |
Synthesis (2): Design Compiler (LN6) |
Synthesis Lab (lab3) |
Synthesis HW (hw4)
due on 11/05; see announcements
if your HW2 design failed synthesis |
--- |
11/05/2010 |
DFT and ATPG (LN7) |
DFT and ATPG Lab (lab4) |
DFT/ATPG HW (hw5)
due on 11/19 |
--- |
11/12/2010 |
Midterm exam
(期中考注意事項;
grades announced) |
--- |
--- |
Proposal Due
by 11/12 (pdf) |
11/19/2010 |
Static Timing Analysis (LN8) |
STA Lab (lab5) |
Verilog HW 4 (hw6)
due on 12/05 (extended) |
--- |
11/26/2010 |
Placement and Routing (LN9) |
P&R Lab 1 (lab6) |
--- |
--- |
12/03/2010 |
Placement and Routing (LN10) |
P&R Lab 2 (lab7) |
P&R HW (hw7)
due on 12/10 (hints) |
--- |
12/10/2010 |
DRC, LVS, LPE (LN11) |
DRC/LVS Lab (lab8)
updated on 12/13 |
--- |
Progress
Report Due |
12/17/2010 |
Verification (LN12) |
Verification Lab (lab9) |
--- |
--- |
12/24/2010 |
FPGA (LN13) |
FPGA Lab (lab10) |
--- |
--- |
12/31/2010 |
Project Presentation (schedule; schedule1231;
簡報注意事項) |
--- |
--- |
Presentation |
01/07/2011 |
Project Presentation (schedule; schedule0107;
簡報注意事項) |
--- |
--- |
Presentation |
01/14/2011 |
Project Presentation (schedule; schedule0114;
簡報注意事項) |
--- |
--- |
Presentation/
Final Report due on 1/17 |