|
Date |
Lecture |
Lab |
Assignment |
Project |
| 09/16/2011 |
Overview (syllabus;
announce;
intro) |
Linux; X-editor (lab0) |
--- |
--- |
| 09/23/2011 |
Verilog (1): Cadence Verilog Language
- Chapter 1-11 |
Verilog Lab 1 (lab1) |
Verilog HW 1 (hw1)
due on 10/7; see
announcements for submission |
--- |
| 09/30/2011 |
Verilog (2): Cadence Verilog Language - Chapter 11-17 |
Verilog Lab 2 (lab2) |
--- |
--- |
| 10/07/2011 |
Verilog (3): Behavior Modeling and
Debugging (LN3-1;
LN3-2) |
--- |
Verilog HW 2 (hw2;errata)
due on 10/21; see
announcements for naming your
design |
--- |
| 10/14/2011 |
Verilog (4): Testbench Writing and
Synthesizable Codes (LN4-1;
LN4-2;
LN4-3) |
--- |
--- |
Topics
Announced (project) |
| 10/21/2011 |
Synthesis (1): Design Compiler (LN5) |
--- |
Verilog HW 3 (hw3)
due on 11/18 (extended); see
announcements before submission |
--- |
| 10/28/2011 |
Synthesis (2): Design Compiler (LN6) |
Synthesis Lab (lab3) |
Synthesis HW (hw4)
due on 11/18 (extended) |
--- |
| 11/04/2011 |
DFT and ATPG (LN7) |
DFT and ATPG Lab (lab4-1, lab4-2) |
DFT/ATPG HW (hw5)
due on 11/18 |
--- |
| 11/11/2011 |
Midterm exam
(special note) |
--- |
--- |
Proposal Due
by 11/11 |
| 11/18/2011 |
Static Timing Analysis (LN8) |
STA Lab (lab5) |
Verilog HW 4 (hw6) |
--- |
| 11/25/2011 |
Placement and Routing (LN9-1;
LN9-2;
LN9-3) |
P&R Lab 1 (lab6;
English instruction lab6-eng) |
--- |
--- |
| 12/02/2011 |
Placement and Routing (LN10-1;
LN10-2) |
P&R Lab 2 (lab7;
English instruction lab7-eng) |
P&R HW (hw7) |
--- |
| 12/09/2011 |
Post-Layout Checking (LN11) |
DRC/LVS Lab (lab8) |
--- |
Progress
Report Due |
| 12/16/2011 |
Verification (LN12) |
Verification Lab (lab9) |
--- |
--- |
| 12/23/2011 |
FPGA (LN13) |
FPGA Lab (lab10) |
--- |
--- |
| 12/30/2011 |
Project Presentation (schedule) |
--- |
--- |
Presentation |
| 01/06/2012 |
Project Presentation (schedule) |
--- |
--- |
Presentation |
| 01/13/2012 |
Project Presentation (schedule) |
--- |
--- |
Presentation/
Final Report due on 1/16 |