Publications
Issued USA Patents
-
USA Patent No. 6,763,513, filed on Jun 26, 2002, Clock Tree Synthesizer for Balancing Reconvergent and Crossover Clock Trees. Handle the most general Reconvergent and Crossover clocks and are later extended to handle multiple output cells and preserved trees with reconvergent and crossover complication.
issued at July 13, 2004.
-
USA Patent No. 6,782,519, filed on Dec 18, 2001, Clock Tree Synthesis for Mixed Domain Clocks. Balancing groups of clocks to achieve minimum group skews.
issued at Aug 24, 2004.
Pending USA Patents
-
App. No. 10/323,432, filed on Dec 18, 2001, Gated Clock Tree Synthesis Handling Gated clock trees in the situation where certain gates have very high number of immediate child gates.
-
App. No. 10/373,327, filed on Feb 24, 2003, Method for Analyzing Path Delays in IC Clock Tree. New MacroModeling technique which accounts for differences in in rise and fall arrival time at the input as well as some other factors.
Book
Journal Publications
Conference Publications
-
``Module assignment for low power,''
J-M. Chang and M. Pedram,
Proc. European Design Automation Conf.,
September 1996, pages 376-381.
-
``Energy minimization using multiple supply voltages,''
J-M. Chang and M. Pedram,
Proc. Symp. on Low Power Electronics and Design,
August 1996, pages 157-162.
-
``Low power register allocation and binding,''
J-M. Chang and M. Pedram,
Proc. 32nd Design Automation Conf.,
pages 29-35, June 1995.
-
``Codex-dp: Co-design of Communicating Systems Using Dynamic Programming,''
J-M. Chang and M. Pedram,
Proc. Design Automation and Test in Europe.,
, March 1999.