Publications

· Chao-Yue (Colby) Lai, Chung-Yang (Ric) Huang, and Kei-Yung Kho, “Improving Constant-Coefficient Multiplier Verification by Partial Product Identification,” Design Automation and Test in Europe (DATE), Munich, Germany, Mar. 2008

· Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang (Ric) Huang, and A. Mishchenko, “Scalable Exploration of Functional Dependency by Interpolation and Incremental SAT Solving,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, USA, Nov. 2007

· Hsing-Chih Hung, Chi-Wen Chang, Tin-Hao Lin, and Chung-Yang (Ric) Huang, “QuteIP: An IP Qualification Framework for System on Chip,” IEEE SoC Conference (SOCC), Hsin-Chu, Taiwan, Aug. 2007

· Chi-An Wu, Ting-Hao Lin, Chih-Chun Lee and Chung-Yang (Ric) Huang, “QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure,” Design Automation and Test in Europe (DATE) Conference, Nice, France, Apr. 2007

§ Feng Lu, Li-C. Wang, K-T. Cheng, and Ric C-Y. Huang ,“A Circuit SAT Solver with Signal Correlation Guided Learning”, Proc. Design Automation & Test Conference in Europe, March 2003.

§ G. Parthasarathy, K-T. Cheng, C-Y Huang, “An Analysis of ATPG and SAT algorithms for Formal Verification”, Proc. International High Level Design Validation and Test Workshop, pp. 177-182, Nov. 2001.

§ R.C.-Y. Huang and K.-T. Cheng, “Using Word-Level ATPG and Modular Arithmetic Constraint-Solving Techniques for Assertion Property Checking”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Volume 20, No. 3, pp. 381-391, March 2001.

§ R.C.-Y. Huang, B. Yang, H.-C. Tsai, and K.-T. Cheng, “Static Property Checking Using ATPG vs. BDD Techniques”, Proc. International Test Conference, pp. 309-316, Oct. 2000.

§ R.C.-Y. Huang and K.-T. Cheng, “Assertion Checking by Combined Word-level ATPG and Modular Arithmetic Constraint-Solving Techniques”, Proc. Design Automation Conference, pp. 118-123, June 2000.

§ S.-Y. Huang, K.-T. Cheng, K.-C. Chen, C.-Y. Huang, and F. Brewer, “AQUILA: An Equivalence Checking System for Large Sequential Designs”, IEEE Trans. on Computer, Vol. 49, No. 5, pp. 443-464, May 2000.

· R.C.-Y. Huang and K.-T. Cheng, “Solving Constraint Satisfiability Problem for Automatic Generation of Design Verification Vectors”, Proc. International High Level Design Validation and Test Workshop, pp. 30-36, Nov. 1999.

· R.C.-Y. Huang and K.-T. Cheng, “A New Extended Finite State Machine (EFSM) Model for RTL Design Verification”, Proc. International High Level Design Validation and Test Workshop, pp. 47-53, Nov. 1998.

· R.C.-Y. Huang, Y. Wang, and K.-T. Cheng, “Libra - A Library-Independent Framework for Post-Layout Performance Optimization”, Proc. International Symposium on Physical Design, pp. 135-140, Apr. 1998.

US Patents

· Chung-Yang (Ric) Huang, "Solving Constraint Satisfiability Problem For Automatic Generation of Design Verification Vectors", No. 60 / 246,422.

- Proposed a word-level ATPG technique that utilizes the high-level design information in ATPG implication and justification algorithms

- Developed a modular arithmetic solver technique to solve the constraints on the datapath circuit

- Proposed a combined word-level ATPG and modular arithmetic solver technique for automatic generation of design verification vectors

· Chung-Yang (Ric) Huang, "Non-Assignable Signal Support During Formal Verification Of Circuit Designs", No. 6618841, Sept. 2003.

- Addressed binary and ternary value system issues in formal verification of circuit designs

- Proposed non-assignable signal concept in ternary verification algorithms

- Developed an efficient algorithm for the ternary verification engine