National Taiwan University, Taipei, Taiwan

Experience Verplex Systems, Inc. / Cadence Design Systems, CA, USA

Senior R&D Manager July 2002 – Feb 2004

R&D Manager Sep 2001 – July 2002

· Led R&D team on the research and development of the core verification techniques (ATPG/BDD/SAT)

· Visited leading semiconductor companies to exchange their functional verification experiences and discuss their design challenges

· Attended major conferences to acquire state-of-the-art verification technologies

· Defined product roadmap and future research directions

· Cooperated with leading research labs and universities (e.g. UCSB, Princeton University, Cadence Berkeley Lab)

Senior Software Engineer Sep 1998 – Sep 2001

Summer Internship June 1998 – Sep 1998

· Researched in the property checking area – proposed a new Extended Finite State Machine (EFSM) model and the word-level ATPG technique

· Initiated the basic framework of BlackTieTM property checker and developed its basic building blocks – circuit modeling, simulation, clock analysis, basic C++ packages, and the formal proof engines

· Conducted experiments on various formal verification engines (ATPG/BDD/SAT) and developed an integrated solution

Avant! Corp., (now Synopsys, Inc.), CA, USA

R&D Internship June 1996 – Sep 1996

June 1997 – Dec 1997

· Researched on post-layout timing optimization using logic restructuring technique

· Developed an integrated post-layout timing optimization approach with various techniques – logic restructuring, buffer insertion, and cell sizing

· Deployed research to Avant!’s timing optimization tool

VLSI Testing, Verification and Synthesis Group, UC Santa Barbara

Research Assistant Apr 1996 – Mar 1999

Teaching Assistant Sep 1995 – Mar 1996

· Applied ATPG-based techniques on (1) post-layout timing optimization, and (2) RTL design verification

· Designed and maintained group website

Dept. Computer Science and Information Engineering, NTU, Taiwan

Teaching Assistant July 1994 – June 1995

· In charge of (1) micro-electronics, (2) digital circuit design, and (3) micro-processor experiments

· Created and compiled the experiment handbooks for the above labs