- General description: This is an entry-level VLSI design course
(to be followed by the course VLSI System Design offered by
Prof. Ming-Fong Chang of the CSIE department),
designed for computer science students.
Unlike traditional VLSI design courses, we will focus not only on
"design" but also on "design automation (computer-aided design)"
which is considered a more computer science oriented area.
- Prerequisites: digital systems, computer organization, data
- Course contents: VLSI design flow, transistor, combinational &
sequential circuit design, subsystem design, design automation
(high-level synthesis, logic synthesis, partitioning, floorplanning,
placement, routing, testing, and simulation).
- Homework: about three to four sets of written homeworks, two
design projects (using Verilog/VHDL on a Xilinx FPGA system), one
mini programming assignment (on router design), and
a final project on design or design automation.
Default final projects selected from the 2001 CAD contest
(hosted by the Ministry of Education) will be provided
so that you may participate in the activity.
- Exam: two midterms on basic concepts
- Grading: Written homework 15%,
design projects (using Schematic & Verilog/VHDL on a Xilinx
design system) 20%,
one programming project (on router design) 10%,
two tests 35%, and
a final project on design or design automation 20% + bonus.
The final scores for graduate and undergraduate students
will be determined separately.