Projects (last update: October 2004)
- Ongoing Projects: Currently we are executing 10 research projects, 6 supported by NSC and 4 by industry.
- Large-Scale Mixed-Sized Cell/Module Placement/Floorplanning (Amount: NTD$970,200/NSC92-2220-E-002-013, NTD$1,508,200/NSC93-2220-E-002-001, NTD$1,431,200/NSC94-2220-E-002-001; November 2003--July 2006; NSC Target Oriented Research Project)
- Integration of Multimedia SOC Systems (Amount: about NTD$1,200,000 per year; April 2004--July 2007; NSC Excellence Project)
- Physical Design for Reconfigurable Systems (Amount: NTD$ 943,900 per year; August 2002--July 2005; NSC 93-2215-E-002-009)
- Gridless Full-Chip Routing for Very-Large Scale Nanometer ICs (Amount: NTD$ 1,256,200/NSC 93-2215-E-002-029; NTD$ 1,286,200/NSC 94-2215-E-002-005; NTD$ 1,337,800/NSC 95-2215-E-002-003; August 2004--July 2007)
- Jumper Insertion for Antenna Avoidance/Fixing(Amount: NTD$ 39,000 per year; August 2004--July 2005; NSC Undergraduate Research Project)
- Spare Cell Selection for Functional Changes (Amount: NTD$ 39,000 per year; August 2004--July 2005; NSC Undergraduate Research Project)
- Floorplanning and Routing for Full-Custom IC Design (Amount: about NTD$ 900,000 per year; October 2003--September 2005; SpringSoft Corp.)
- Comprehensive Environment for PCB Design: Part I: Design Rule Checker & Router(Amount: NTD$ 1,000,000 per year; March 2004--February 2007; Quanta Corp.)
- Physical Design for Nanometer IC Design (Amount: about NTD$ 800,000 per year; August 2004--July 2007; UMC Corp.)
- Routing for Flip-Chip Design (Amount: about NTD$ 800,000 per year; October 2004--September 2005; Faraday Corp.)
- Power/Signal Integrity Design Methodology (Amount: NTD$ 1,200,000 per year; December 2003--November 2006; RealTek Corp.; pending)
- Completed Projects
- Area, Timing, Power, and Noise Optimization Under the Transmission Line Model (Amount: NTD$801,600 per year; August 2002--July 2004; NSC 91-2215-E-002-036)
- Placement for Flip-Chip Design (Amount: NTD$ 39,000 per year; August 2003--July 2004; NSC Undergraduate Research Project)
- Performance Optimization Under the Transmission Line Model (Amount: NTD$792,700; August 2001--July 2002; NSC 90-2215-E-002-048)
- Floorplanning for System-on-Chip Design (Amount: NTD$730,000; August 2000--July 2001; NSC 89-2215-E-009-117)
- Interconnect-driven Floorplanning (Amount: USD$25,000; April 2000--March 2001; Arcadia Design Systems, San Jose, CA)
- Crosstalk-oriented Interconnect Optimization (Amount: NTD$39,000; Project for undergraduate students; August 1999--July 2000; NSC89-2815-C-009-039-E)
- MB*-tree: An Interconnect-driven Floorplanning System for Large-Scale Modules Based on Multilevel B*-Trees (Amount: USD$15,000; September 2001--August 2002; Intel Corporation, OR, USA)
- Simultaneous Interconnect Area, Delay, Power, and Noise Optimization for Systems-on-a-chip Design (Amount: NTD$589,300; August 1999--July 2000; NSC 89-2215-E-009-055)
- Unified Design of Router and Segmentation Architecture for Field-Programmable Systems-on-a-Chip (Amount: NTD$434,600; August 1999--July 2000; NSC 89-2215-E-009-054)
- Routability Analysis of FPGA Switch Modules (finished; 1997; NSC 86-2621-E-009-019-T)
- Design and Analysis of Symmetric Array-Based FPGA Segmentations (finished; August 1997--July 1998; NSC 87-2215-E-009-041)
- Design and Analysis of FPD Universal Switch Modules (finished; August 1998--July 1999; NSC 88-2215-E-009-064)
- Crosstalk in Deep-submicron Technologies (finished; August 1998--July 1999; NSC 88-2218-E-009-056)
- Advanced Microprocessor Design (July 1998--Dec 1999; NSC, UMC, MXIC, etc;
NSC 88-2622-E-009-004)