IEDM/VLSI
2025 2024 2023 2022 2021 2020 2019 2018 2017 2016 2014 2012 2010 2009 2007 2005 2004 2003 2002 1999
2025
  • Bo-Wei Huang, Ying-Qi Liu, Ching-Wang Yao, Wei-Jen Chen, Min-Kuan Lin, Xin-Yuan Lin, Chun-Yi Cheng, Yi Huang, Ding-Wei Lin, Chih-Hsuan Lu, Tsung-Han Tsai, and C. W. Liu, “First Demonstration of Monolithic 3-Tier Nanosheet Transistor Stacking with Split Gate Featuring Tri-State Inverter/Half SRAM Functionalities,” Symposium on VLSI Technology and Circuits (VLSI), June 8-12, 2025.
  • Tao Chou, He-Wen Shen, Yu-Sheng Lai, Chia-Wei Tseng, Fang-Yu Chang, Hsin-Cheng Lin, Ching-Wang Yao, and C. W. Liu, “Unified Physics-Based CFET Thermal SPICE Considering BEOL, Substrate, and BSPDN Using Adiabatic Cones,” Symposium on VLSI Technology and Circuits (VLSI), June 8-12, 2025.
  • Yu-Shan Wu, Yuan-Ming Liu, Hsien-Ming Sung, Rong-Wei Ma, Johannes Gracia, Hidenari Fujiwara, Kuan-Wei Lu, and C. W. Liu, “First Demonstration of 2-Floor GAA In2O3 Nanosheet FET Enabled by TiN Sacrificial Layers and Fluorine Passivation,” Symposium on VLSI Technology and Circuits (VLSI), June 8-12, 2025.
  • Jhih-Yuan Liang, Yu-Rui Chen, Guan-Hua Chen, Yun-Wen Chen, Yu-An Chen, Bo-Hui Yu, Yan-Jyun Chen, and C. W. Liu, “Stacked AFE-Like/FE HZO (4.5nm) to Achieve 0.75V Operating Voltage and Record Endurance Exceeding 7E12 Using Water Quenching and TiN Top Electrodes,” Symposium on VLSI Technology and Circuits (VLSI), June 8-12, 2025.
2024
  • Bo-Wei Huang, Chun-Yi Cheng, Wan-Hsuan Hsieh, Yu-Rui Chen, Wei-Jen Chen, Yi-Chun Liu, Min-Kuan Lin, Ying-Qi Liu, Hao-Yi Lu, Yi Huang, Ding-Wei Lin, and C. W. Liu, “WNxCy VT Tuning of Split Gate Nanosheet CFET with Dual Work Function Metals Achieving 0.93 VT Match/ Improved 0.24V Noise Margin/ Record Gain of 61V/V,” International Electron Devices Meeting (IEDM), Dec. 7-11, 2024.
  • (Highlight paper) Guan-Hua Chen, Yu-Tsung Liao, Zefu Zhao, Yu-Rui Chen, Yun-Wen Chen, Wei-Jen Chen, Wei-Teng Hsu, Hao-Yi Lu, Ming-Chang Liu, Yu-An Chen, and C. W. Liu, “Uniform and Fatigue-Free Ferroelectric HZO with Record EBD of 6.3MV/cm and Record Final 2Pr of 64μC/cm2 at Record 5E12 Endurance Using Low Lattice Misfit (2.9%) β-W,” International Electron Devices Meeting (IEDM), Dec. 7-11, 2024.
  • C.-H. Liu, K.-Y. Hsiang, F.-S. Chang, Y.-T. Chang, C. W. Liu, and M. H. Lee, “Energy Material for Extreme Environment: Unveiling Novel Self-Resilience of Hf1-xZrxO2 for Electrostatic Energy Storage (EES) and Pyroelectric Energy Harvesting (PEH),” accepted by International Electron Devices Meeting (IEDM), Dec. 7-11, 2024.
  • Zefu Zhao, Yu-Rui Chen, Yu-Tsung Liao, Yun-Wen Chen, Wan-Hsuan Hsieh, Jer-Fu Wang, Yu-An Chen, Hao-Yi Lu, Wei-Teng Hsu, Dai-Ying Lee, Ming-Hsiu Lee, and C. W. Liu, “Engineering HZO by Flat Amorphous TiN with 0.3nm Roughness Achieving Uniform c-axis Alignment, Record High Breakdown Field (~10nm HZO), and Record Final 2Pr of 56 uC/cm2 with Endurance > 4E12,” accepted by Symposium on VLSI Technology and Circuits (VLSI), 2024.
2023
  • Chien-Te Tu, Wan-Hsuan Hsieh, Yu-Rui Chen, Bo-Wei Huang, Yu-Tsung Liao, Wei-Jen Chen, Yi-Chun Liu, Chun-Yi Cheng, Hung-Chun Chou, Hao-Yi Lu, Cheng-Hsien Hsin, Geng-Min He, Dong Soo Woo, Shee-Jier Chueh, and C. W. Liu, “First Demonstration of Monolithic Self-aligned Heterogeneous Nanosheet Channel Complementary FETs with Matched VT by Band Alignments of Individual Channels,” International Electron Devices Meeting (IEDM), Dec. 9-13, 2023.
  • K.-Y. Hsiang, J.-Y. Lee, F.-S. Chang, Z.-F. Lou, Z.-X. Li, Z.-H. Li, J.-H. Chen, C. W. Liu, T.-H. Hou, and M. H. Lee, “FeRAM Recovery up to 200 Periods with Accumulated Endurance 1012 Cycles and an Applicable Array Circuit toward Unlimited eNVM Operations,” Symposium on VLSI Technology and Circuits (VLSI), JUNE 11-16, 2023.
  • J.-Y. Lee, F.-S. Chang, K.-Y. Hsiang, P.-H. Chen, Z.-F. Luo, Z.-X. Li, J.-H. Tsai, C. W. Liu, and M. H. Lee, “3D Stackable Vertical Ferroelectric Tunneling Junction (V-FTJ) with on/off Ratio 1500x, Applicable Cell Current, Self-Rectifying Ratio 1000x, Robust Endurance of 109 Cycles, Multilevel and Demonstrated Macro Operation Toward High-Density BEOL NVMs.” Symposium on VLSI Technology and Circuits (VLSI), JUNE 11-16, 2023.
  • Yi-Chun Liu, Yu-Rui Chen, Yun-Wen Chen, Hsin-Cheng Lin, Wan-Hsuan Hsieh, Chien-Te Tu, Bo-Wei Huang, Wei-Jen Chen, Chun-Yi Cheng, Shee-Jier Chueh, and C. W. Liu, “Extremely High-k Hf0.2Zr0.8O2 Gate Stacks Integrated into Ge0.95Si0.05 Nanowire and Nanosheet nFETs Featuring Respective Record ION per Footprint of 9200μA/μm and Record ION per Stack of 360μA at VOV=VDS=0.5V,” Symposium on VLSI Technology and Circuits (VLSI), JUNE 11-16, 2023.
  • Yu-Rui Chen, Yi-Chun Liu, Zefu Zhao, Wan-Hsuan Hsieh, Jia-Yang Lee, Chien-Te Tu, Bo-Wei Huang, Jer-Fu Wang, Shee-Jier Chueh, Yifan Xing, Guan-Hua Chen, Hung-Chun Chou, Dong Soo Woo, M. H. Lee, and C. W. Liu, “First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles,” Symposium on VLSI Technology and Circuits (VLSI), JUNE 11-16, 2023.
  • Zefu Zhao, Yu-Rui Chen, Yun-Wen Chen, Wan-Hsuan Hsieh, Jer-Fu Wang, Jia-Yang Lee, Yifan Xing, Guan-Hua Chen, and C. W. Liu, “Towards Epitaxial Ferroelectric HZO on n+-Si/Ge Substrates Achieving Record 2Pr = 84 μC/cm2 and Endurance > 1E11,” Symposium on VLSI Technology and Circuits (VLSI), JUNE 11-16, 2023.
  • Jih-Chao Chiu, Eknath Sarkar, Yuan-Ming Liu, Yu-Ciao Chen, Yu-Cheng Fan, and C. W. Liu, “First Demonstration of a-IGZO GAA Nanosheet FETs Featuring Achievable SS=61 mV/dec, Ioff=1E-7uA/um, DIBL=44 mV/V, Positive VT, and Process Temp. of 300 oC,” Symposium on VLSI Technology and Circuits (VLSI), JUNE 11-16, 2023.
2022
  • Chien-Te Tu, Yi-Chun Liu, Bo-Wei Huang, Yu-Rui Chen, Wan-Hsuan Hsieh, Chung-En Tsai, Shee-Jier Chueh, Chun-Yi Cheng, Yichen Ma, and C. W. Liu, “First Demonstration of Monolithic 3D Self-aligned GeSi Channel and Common Gate Complementary FETs by CVD Epitaxy Using Multiple P/N Junction Isolation,” accepted by International Electron Devices Meeting (IEDM), 2022.
  • C.-Y. Liao, Z.-F. Lou, C.-Y. Lin, A. Senapati, R. Karmakar, K.-Y. Hsiang, Z.-X. Li, W.-C. Ray, J.-Y. Lee, P.-H. Chen, F.-S. Chang, H.-H. Tseng, C.-C. Wang, J.-H. Tsai, Y.-T. Tang, S. T. Chang, C. W. Liu, S. Maikap, and M. H. Lee, “Superlattice HfO2-ZrO2 based Ferro-Stack HfZrO2 FeFETs: Homogeneous-Domain Merits Ultra-Low Error, Low Programming Voltage 4 V and Robust Endurance 109 cycles for Multibit NVM,” accepted by International Electron Devices Meeting (IEDM), 2022.
  • H.-L. Chiang, J.-F. Wang, K.-H. Lin, C.-H. Nien, J.-J. Wu, K.-Y. Hsiang, C.-P. Chuu, Y.-W. Chen, X.W. Zhang, C. W. Liu, Tahui Wang, C.-C. Wang, M.-H. Lee, M.-F. Chang, C.-S. Chang, and T.C. Chen, “Interfacial-Layer Design for Hf1-xZrxO2-Based FTJ Devices: From Atom to Array,” accepted by Symposium on VLSI Technology and Circuits (VLSI), 2022.
  • Chung-En Tsai, Chun-Yi Cheng, Bo-Wei Huang, Hsin-Cheng Lin, Tao Chou, Chien-Te Tu, Yi-Chun Liu, Sun-Rong Jan, Yu-Rui Chen, Wan-Hsuan Hsieh, Kung-Ying Chiu, Shee-Jier Chueh, and C. W. Liu, “Nearly Ideal Subthreshold Swing and Delay Reduction of Stacked Nanosheets Using Ultrathin Bodies,” accepted by Symposium on VLSI Technology and Circuits (VLSI), 2022.
2021
  • (Roger A. Haken Best Student Paper Award, the first winner from Taiwan) IEDM Roger A. Haken Best Student Paper Award Winner
     Chung-En Tsai, Yi-Chun Liu, Chien-Te Tu, Bo-Wei Huang, Sun-Rong Jan, Yu-Rui Chen, Jyun-Yan Chen, Shee-Jier Chueh, Chun-Yi Cheng, Chia-Jung Tsen, Yichen Ma, and C. W. Liu, “Highly Stacked 8 Ge0.9Sn0.1 Nanosheet pFETs with Ultrathin Bodies (~3nm) and Thick Bodies (~30nm) Featuring the Respective Record ION/IOFF of 1.4x107 and Record ION of 92μA at VOV=VDS= -0.5V by CVD Epitaxy and Dry Etching,” pp. 569-572, International Electron Devices Meeting (IEDM), 2021.
  • (Highlight paper) Yi-Chun Liu, Chien-Te Tu, Chung-En Tsai, Yu-Rui Chen, Jyun-Yan Chen, Sun-Rong Jan, Bo-Wei Huang, Shee-Jier Chueh, Chia-Jung Tsen, and C. W. Liu, “First Highly Stacked Ge0.95Si0.05 nGAAFETs with Record ION = 110 μA (4100 μA/μm) at VOV=VDS=0.5V and High Gm,max = 340 μS (13000 μS/μm) at VDS=0.5V by Wet Etching,” Symposia on VLSI Technology and Circuits (VLSI), 2021.
  • Chung-En Tsai, Yu-Rui Chen, Chien-Te Tu, Yi-Chun Liu, Jyun-Yan Chen, and C. W. Liu, “First Demonstration of Multi-VT Stacked Ge0.87Sn0.13 Nanosheets by Dipole-Controlled ALD WNxCy Work Function Metal with Low Resistivity and Thermal Budget ≤ 400 °C,” Symposia on VLSI Technology and Circuits (VLSI), 2021.
  • (Highlight paper) Ya-Jui Tsou, Kai-Shin Li, Jia-Min Shieh, Wei-Jen Chen, Hsiu-Chih Chen, Yi-Ju Chen, Cho-Lun Hsu, Yao-Min Huang, Fu-Kuo Hsueh, Wen-Hsien Huang, Wen-Kuan Yeh, Huan-Chi Shih, Pang-Chun Liu, C. W. Liu, Yu-Shen Yen, Chih-Huang Lai, Jeng-Hua Wei, Denny D. Tang, and Jack Yuan-Chen Sun, “First Demonstration of Interface-Enhanced SAF Enabling 400oC-Robust 42 nm p-SOT-MTJ Cells with STT-Assisted Field-Free Switching and Composite Channels,” Symposia on VLSI Technology and Circuits (VLSI), 2021.
  • H.L. Chiang, J.F. Wang, T.C. Chen, T.W. Chiang, C. Bair, C.Y. Tan, L.J. Huang, H.W. Yang, J.H. Chuang, H.Y. Lee, K. Chiang, K.H. Sheng, Y.J. Lee, R. Wang, C. W. Liu, T. Wang, X. Bao, E. Wang, J. Cai, C.T. Lin, H. Chuang, H.S.P. Wong, M.F. Chang, “Cold MRAM as a Density Booster for Embedded NVM in Advanced Technology,” Symposia on VLSI Technology and Circuits (VLSI), 2021.
2020
  • Yu-Shiang Huang, Chung-En Tsai, Chien-Te Tu, Jyun-Yan Chen, Hung-Yu Ye, Fang-Liang Lu, and C. W. Liu, “First Demonstration of Uniform 4-Stacked Ge0.9Sn0.1 Nanosheets with Record ION=78uA at VOV=VDS= -0.5V and Low Noise Using Double Ge0.95Sn0.05 Caps, Dry Etch, Low Channel Doping, and High S/D Doping,” accepted by International Electron Devices Meeting (IEDM), 2020.
  • Yu-Shiang Huang, Fang-Liang Lu, Chien-Te Tu, Jyun-Yan Chen, Chung-En Tsai, Hung-Yu Ye, Yi-Chun Liu and C. W. Liu, “First Demonstration of 4-Stacked Ge0.915Sn0.085 Wide Nanosheets by Highly Selective Isotropic Dry Etching with High S/D Doping and Undoped Channels,” Symposia on VLSI Technology and Circuits (VLSI), 2020.
  • Chia-Che Chung, Hsin-Cheng Lin, H. H. Lin, W. K. Wan, M.-T. Yang, and C. W. Liu, “Interpretable Neural Network to Model and to Reduce Self-Heating of FinFET Circuitry,” Symposia on VLSI Technology and Circuits (VLSI), 2020.
  • Fang-Liang Lu, Yi-Chun Liu, Chung-En Tsai, Hung-Yu Ye, and C. W. Liu, “Record Low Contact Resistivity to Ge:B (8.1x10-10Ω-cm2) and GeSn:B (4.1x10-10Ω-cm2) with Optimized [B] and [Sn] by In-situ CVD Doping,” Symposia on VLSI Technology and Circuits (VLSI), 2020.
2019
  • Yu-Shiang Huang, Chung-En Tsai, Chien-Te Tu, Hung-Yu Ye, Yi-Chun Liu, Fang-Liang Lu, and C. W. Liu, “First Stacked Ge0.88Sn0.12 pGAAFETs with Cap, LG=40nm, Compressive Strain of 3.3%, and High S/D Doping by CVD Epitaxy Featuring Record ION of 58mA at VOV=VDS= -0.5V, Record Gm,max of 172mS at VDS= -0.5V, and Low Noise,” pp. 689-692, International Electron Devices Meeting (IEDM), 2019.
  • Chien-Te Tu, Yu-Shiang Huang, Fang-Liang Lu, Hsiao-Hsuan Liu, Chung-Yi Lin, Yi-Chun Liu, and C. W. Liu, “First Vertically Stacked Tensily Strained Ge0.98Si0.02 nGAAFETs with No Parasitic Channel and LG = 40 nm Featuring Record ION = 48 mA at VOV=VDS=0.5V and Record Gm,max(mS/mm)/SSSAT(mV/dec) = 8.3 at VDS=0.5V,” pp. 681-684, International Electron Devices Meeting (IEDM), 2019.
  • Ya-Jui Tsou, Chia-Che Chung, Jih-Chao Chiu, Huan-Chi Shih, and C. W. Liu, “Thermal and Reliability Modeling of FinFET-Driven STT-pMTJ Array Considering Mutual Coupling, 3D Heat Flow, and BEOL Effects,” IEDM MRAM Poster, 2019.
  • Jih-Chao Chiu, Ya-Jui Tsou, Huan-Chi Shih, and C. W. Liu, “Write Error Rate Prediction of STT-pMTJ Considering Process Variations and Thermal Fluctuations,” IEDM MRAM Poster, 2019.
  • Min-Hung Lee, Kuan-Ting Chen, Chun-Yu Liao, Guo-Yu Siang, Chieh Lo, Hong-Yu Chen, Yi-Ju Tseng, Chung-Yu Chueh, Ching Chang, Yen-Yun Lin, Yu-Jun Yang, F-C Hsieh, Shu-Tong Chang, Ming-Han Liao, Kai-Shin Li, and C. W. Liu, “Bi-directional Sub-60mV/dec, Hysteresis-Free, Reducing Onset Voltage and High Speed Response of Ferroelectric-AntiFerroelectric Hf0.25Zr0.75O2 Negative Capacitance FETs,” pp. 566-569, International Electron Devices Meeting (IEDM), 2019.
  • Yu-Shiang Huang, Hung-Yu Ye, Fang-Liang Lu, Yi-Chun Liu, Chien-Te Tu, Chung-Yi Lin, Shih-Ya Lin, Sun-Rong Jan, C. W. Liu, “First Vertically Stacked, Compressively Strained, and Triangular Ge0.91Sn0.09 pGAAFETs with High ION of 19.3mA at VOV=VDS=-0.5V, Gm of 50.2mS at VDS=-0.5V and Low SSlin of 84mV/dec by CVD Epitaxy and Orientation Dependent Etching,” 2019 Symposia on VLSI Technology and Circuits, p.T14-3, Kyoto, Japan, June 9-14, 2019.
  • Fang-Liang Lu, Chung-En Tsai, Chih-Hsiung Huang, Hung-Yu Ye, Shih-Ya Lin, C. W. Liu, “Record Low Contact Resistivity (4.4x10-10Ω-cm2) to Ge Using In-situ B and Sn Incorporation by CVD With Low Thermal Budget (≤400℃) and Without Ga,” 2019 Symposia on VLSI Technology and Circuits, p. T14-2, Kyoto, Japan, June 9-14, 2019.
2018
  • M. H. Lee, K.-T. Chen, C.-Y. Liao, S.-S. Gu, G.-Y. Siang, Y.-C. Chou, H.-Y. Chen, J. Le, R.-C. Hong, Z.-Y. Wang, S.-Y. Chen, P.-G. Chen, M. Tang, Y.-D. Lin, H.-Y. Lee, K.-S. Li, and C. W. Liu, “Extremely Steep Switch of Negative-Capacitance Nanosheet GAA-FETs and FinFETs,” IEEE International Electron Devices Meeting (IEDM), San Francisco, California, Dec. 1-5, 2018.
  • Zong-You Luo, Ya-Jui Tsou, and C. W. Liu, “Field-Free Spin-Orbit Torque Switching of pMTJ Utilizing Voltage-Controlled Magnetic Anisotropy and STT,” IEDM MRAM workshop, San Francisco, California, Dec. 1-6, 2018.
  • Ya-Jui Tsou, Zong-You Luo, Chia-Che Chung, and C. W. Liu, “Thermal Modeling of FinFET-Driven Spin-Orbit Torque MRAM Considering Thermal Coupling and BEOL Effects,” IEDM MRAM workshop, San Francisco, California, Dec. 1-6, 2018.
  • Jhih-Yang Yan, Chia-Che Chung, Sun-Rong Jan, H. H. Lin, W. K. Wan, M.-T. Yang, and C. W. Liu, "Comprehensive Thermal SPICE Modeling of FinFETs and BEOL with Layout Flexibility Considering Frequency Dependent Thermal Time Constant, 3D Heat Flows, Boundary/Alloy Scattering, and Interfacial Thermal Resistance with Circuit Level Reliability Evaluation," Symposium on VLSI Technology (VLSI-Technology), Honolulu , Hawaii, June 18-22, 2018.
2017
  • Yu-Shiang Huang, Fang-Liang Lu, Ya-Jui Tsou, Chung-En Tsai, Chung-Yi Lin, Chih-Hao Huang, and C. W. Liu, “First Vertically Stacked GeSn Nanowire pGAAFETs with Ion=1850mA/mm (VOV=VDS=-1V) on Si by GeSn/Ge CVD Epitaxial Growth and Optimum Selective Etching,” p.832-835, International Electron Devices Meeting (IEDM), 2017.
  • M. H. Lee, P.-G. Chen, S.-T. Fan, Y.-C. Chou, C.-Y. Kuo, C.-H. Tang, H.-H. Chen, S.-S. Gu, R.-C. Hong, Z.-Y. Wang, S.-Y. Chen, C.-Y. Liao, K.-T. Chen, S. T. Chang, M.-H. Liao, K.-S. Li, and C. W. Liu, “Ferroelectric Al:HfO2 Negative Capacitance FETs,” p.565-568, International Electron Devices Meeting (IEDM), 2017.
2016
  • Jhih-Yang Yan, Sun-Rong Jan, Yu-Jiun Peng, H. H. Lin, W. K. Wan, Y.-H. Huang, Bigchoug Hung, K.-T. Chan, Michael Huang, M.-T. Yang, and C. W. Liu, “Thermal Resistance Modeling of Back-end Interconnect and Intrinsic FinFETs, and Transient Simulation of Inverters with Capacitive Loading Effects,” p.898-901, International Electron Devices Meeting (IEDM), 2016.
  • Yu-Shiang Huang, Chih-Hsiung Huang, Fang-Liang Lu, Chung-Yi Lin, Hung-Yu Ye,I-Hsieh Wong, Sun-Rong Jan, Huang-Siang Lan, C. W. Liu, Yi-Chiau Huang, Hua Chung, Chorng-Ping Chang, Schubert S. Chu, and Satheesh Kuppurao “Record High Mobility (428cm2/V-s) of CVD-grown Ge/Strained Ge0.91Sn0.09 /Ge Quantum Well p-MOSFETs,” p.822-825, International Electron Devices Meeting (IEDM), 2016.
  • I-Hsieh Wong, Fang-Liang Lu, Shih-Hsien Huang, Hung-Yu Ye, Chun-Ti Lu, Jhih-Yang Yan, Yu-Cheng Shen, Yu-Jiun Peng, Huang-Siang Lan, and C. W. Liu, “High Performance Ge Junctionless Gate-all-around NFETs with Simultaneous Ion =1235 mA/mm at VOV=VDS=1V, SS=95 mV/dec, high Ion/Ioff=2E6, and Reduced Noise Power Density using S/D Dopant Recovery by Selective Laser Annealing,” p.842-845, International Electron Devices Meeting (IEDM), 2016.
  • M. H. Lee, S.-T. Fan , C.-H. Tang , P.-G. Chen, Y.-C. Chou , H.-H. Chen , J.-Y. Kuo , M.-J. Xie, S.-N. Liu , M.-H. Liao , C.-A. Jong , K.-S. Li , M.-C. Chen , and C. W. Liu, "Physical Thickness 1.x nm Ferroelectric HfZrOx Negative Capacitance FETs,” p.306-309, International Electron Devices Meeting (IEDM), 2016.
2014
  • I-Hsieh Wong, Yen-Ting Chen, Shih-Hsien Huang, Wen-Hsien Tu, Yu-Sheng Chen, Tai-Cheng Shieh, Tzu-Yao Lin, Huang-Siang Lan, and C. W. Liu, “In-situ Doped and Tensily Stained Ge Junctionless Gate-all-around nFETs on SOI Featuring Ion = 828 uA/um, Ion/Ioff ~ 1E5, DIBL= 16-54 mV/V, and 1.4X External Strain Enhancement” p.239-242, International Electron Devices Meeting (IEDM), 2014.
2012
  • C.-H. Shen, J.-M. Shieh, T.-T. Wu, U.-P. Chiou, H.-C. Kuo, P. Yu, T.-C. Lu, Y.-L. Chueh, C. W. Liu, C. Hu, and F.-L. Yang, “Hybrid CIS/Si Near-IR Sensor and 16% PV Energy-Harvesting Technology,” p.279-282, International Electron Devices Meeting (IEDM), 2012.
  • Shu-Han Hsu, Hung-Chih Chang, Chun-Lin Chu, Yen-Ting Chen, Wen-Hsien Tu, Fu Ju Hou, Chih Hung Lo, Po-Jung Sung, Bo-Yuan Chen, Guo-Wei Huang, Guang-Li Luo, C. W. Liu, Chenming Hu, and Fu-Liang Yang, “Triangular-channel Ge NFETs on Si with (111) Sidewall-Enhanced Ion and Nearly Defect-free Channels,” p.525-528, International Electron Devices Meeting (IEDM), 2012.
  • Cheng-Ming Lin, Hung-Chih Chang, Yen-Ting Chen, I-Hsieh Wong, Huang-Siang Lan, Shih-Jan Luo, Jing-Yi Lin, Yi-Jen Tseng, C. W. Liu, Chenming Hu, and Fu-Liang Yang, “Interfacial layer-free ZrO2 on Ge with 0.39-nm EOT, κ~43, ~2×10-3 A/cm2 gate leakage, SS =85 mV/dec, Ion/Ioff =6×105, and high strain response,” p.509-512, International Electron Devices Meeting (IEDM), 2012.
  • C. -M. Lin, Y. -T. Chen, H. -C. Chang, H. -S. Lan, I. -H. Wong, S. -J. Luo, J. -Y. Lin, C. W. Liu, Chenming Hu, and Fu-Liang Yang, “ Ge n-MOSFETs using Low Leakage 1nm EOT ZrO2 Gate Dielectrics Nearly Free of Interfacial Layer,” submitted to Symposium on VLSI Technology (VLSIT), 2012.
  • Y. -T. Chen, H. -S. Lan, C. -M. Lin, H. -C. Chang, W. -H. Tu, J. -Y. Lin, I. -H. Wong, S. -J. Luo, C. W. Liu, Chenming Hu, and Fu-Liang Yang, “ Strain Response and Doping-dependent Peak Mobility of High Performance Ge (111) n-MOSFETs,” submitted to Symposium on VLSI Technology (VLSIT), 2012.
2010
  • Yen Chun Fu, William Hsu, Yen-Ting Chen, Huang-Siang Lan, Cheng-Han Lee, Hung-Chih Chang, Hou-Yun Lee, Guang-Li Luo, Chao-Hsin Chien, C. W. Liu, Chenming Hu, and Fu-Liang Yang “ High mobility high on/off ratio C-V dispersion-free Ge n-MOSFETs and their strain response,” International Electron Devices Meeting (IEDM), 2010.
2009
  • G.-L. Luo, S.-C. Huang, C.-T. Chung, Dawei Heh, C.-H. Chien, C.-C. Cheng, Y.-J. Lee, W.-F. Wu, C.-C. Hsu, M.-L. Kuo, J.-Y. Yao, M.-N. Chang, C. W. Liu, C.-M. Hu, C.-Y. Chang, and F.-L. Yang, “A Comprehensive Study of Ge1-xSix on Ge for the Ge nMOSFETs with Tensile Stress, Shallow Junctions and Reduced Leakage,” IEDM, Baltimore, 2009.
2007
  • T.-H. Cheng, C. T. Lee, M. H. Liao, P. -S. Kuo, T. A. Hung, and C. W. Liu, “Electrically pumped Ge Laser at room temperature,” International Electron Devices Meeting (IEDM), Washington D.C., Dec. 2007.
2005
  • M. H. Liao, C.-Y. Yu, C.-F. Huang, C.-H. Lin, C.-J. Lee, M.-H. Yu, S. T. Chang, C.-Y. Liang, C.-Y. Lee, T.-H. Guo, C.-C. Chang, and C. W. Liu, “2um emission from Si/Ge heterojunction LED and up to 1.55 um detection by GOI detector with strain-enhanced features,” 51st International Electron Devices Meeting (IEDM), Washington D.C., 2005.
2004
  • S. Maikap, M. H. Liao, F. Yuan, M. H. Lee, C.-F. Huang, S. T. Chang, and C. W. Liu, “Package-strain-enhanced device and circuit performance,” 50th International Electron Devices Meeting (IEDM), pp. 233-236, San Francisco, Dec. 13-15, 2004.
2003
  • M. H. Lee, P. S. Chen, W.-C. Hua, C.-Y. Yu, Y. T. Tseng, S. Maikap, Y. M. Hsu, C. W. Liu, S. C. Lu, and M.-J. Tsai, “Comprehensive Low-Frequency and RF Noise Characteristics in Strained-Si NMOSFETs,” pp. 69-72, International Electron Devices Meeting (IEDM), 2003.
2002
  • B.-C. Hsu, S. T. Chang, C.-R. Shie, C.-C. Lai, P. S. Chen, and C. W. Liu, “High Efficient 820 nm MOS Ge Quantum Dot Photodetectors for Short Reach Integrated Optical Receivers,” pp. 91-94, International Electron Devices Meeting (IEDM), 2002.
  • Z. Pei, C. S. Liang, L. S. Lai, Y. T. Tseng, Y. M. Hsu, P. S. Chen, S. C. Lu, C. M. Liu, M.-J. Tsai and C. W. Liu, “High Efficient 850nm and 1310nm Multiple Quantum Well SiGe/Si Heterojunction Phototransistors with 1.25 Plus GHz Bandwidth,” pp. 297-300, International Electron Devices Meeting (IEDM), 2002.
1999
  • C. W. Liu, M. H. Lee, C.-F. Lin, I. C. Lin, W. T. Liu, and H. H. Lin,”Light Emission and Detection by Metal Oxide Silicon Tunneling Diodes,” pp. 749-752, International Electron Devices Meeting (IEDM), 1999.