read_file -format verilog {./CTE.v}
create_clock -name "clk" -period 10 -waveform { 0 5  }  { clk  }
set_dont_touch_network  [ find clock clk ]
set_fix_hold  [ find clock clk]
set_operating_conditions "typical" -library "typical"
set_wire_load_model -name "ForQA" -library "typical"
set_wire_load_mode "segmented"

set_input_delay -clock clk 2 reset
set_input_delay -clock clk 2 op_mode
set_input_delay -clock clk 2 in_en
set_input_delay -clock clk 2 yuv_in[*]
set_input_delay -clock clk 2 rgb_in[*]

set_output_delay -clock clk 2 rgb_out[*]
set_output_delay -clock clk 2 yuv_out[*]
set_output_delay -clock clk 2 busy
set_output_delay -clock clk 2 out_valid

set_boundary_optimization "*"
set_fix_multiple_port_nets -all -buffer_constants
set_max_area 0
set_max_fanout 8 CTE
set_max_transition 1 CTE
uplevel #0 check_design
compile -exact_map
uplevel #0 { report_timing -path full -delay max -nworst 1 -max_paths 1 -significant_digits 2 -sort_by group }
uplevel #0 { report_power -analysis_effort low }
uplevel #0 { report_area -nosplit }
write -hierarchy -format ddc -output ./CTE.ddc
write -hierarchy -format verilog -output ./CTE_syn.v
write_script > ./CTE.dc
write_sdf -version 2.1 CTE.sdf


read_lib HSs13n_512x8_fast_syn.lib 
write_lib HSs13n_512x8 -output HSs13n_512x8_fast_syn.db
read_lib HSs13n_512x8_slow_syn.lib 
write_