Joining the Electronic Design Automation (EDA) Lab?
General Information
- Bring your smiles and a copy of your transcript
for interview.
- You are free to quit anytime if admitted to our group.
3 NOs policy: No question asked, no side effect, no ...!
- Typically, I admit 4 M.S. students per year. According to the
rule in our EDA group, I will need to take at least three ºÓ¤h¦Ò¸Õ¥Í
every four years.
- Notice that I am with both the EDA group and
the Computer Science (CS)
group. So you might want to apply to both groups to optimize
your chance of entering our lab since my quotas in both groups are
limited and are typically not sufficient for those who request to
join our lab.
- I strongly suggest that you talk to my students about the details of
our group before interviewing with me. Their contact information is
available at
the EDA lab at NTU.
- Typically, I don't accept students at the first interview. I
strongly recommend that you really think it over after interview
about your suitability for this lab.
General Requirements
- High EQ, self-motivated, interested in VLSI software and hardware design,
adequate programming skills, and willing to work hard
(background knowledge: logic design, data structures).
- Our group is ABSOLUTELY NOT suitable for you if
- you don't have strong sense of responsibility,
- you often need somebody to push you for doing research and other matters,
- you are a so-so guy and just want to do so-so jobs (no intention
to optimize your work/performance),
- you cannot or don't want to get along with others well, or
- you plan to stay in school for a long time (our current average times
are about 4 years for the Ph.D. degree and 2 years for the M.S. degree; if you
plan to study for a longer time (e.g., 7 years) for the Ph.D. degree,
our group is definitely NOT a right place for you).
M.S. Program Requirements
- On-campus course requirements: (1) VLSI Physical Design,
(2) Algorithms, (3) CAD Flow (core course of GIEE), (4) VLSI Design,
(5) Two more courses on VLSI related topics (e.g., VLSI testing, simulation,
logic synthesis, formal verification, design for manufacturing,
etc),
(6) One course on mathematics or optimization theory (such as graph algorithms,
combinatorial optimization, linear and nonlinear programming,
computational geometry, numerical methods, or operations research),
(7) English technical writing (finish this course in the
first year).
(I hope this can solidify your VLSI software as well as hardware
training.)
- Off-campus course requirements: Selected training courses
offered at CIC (Chip Implementation Center) in Hsinchu
during winter or summer breaks (for learning commercial CAD
tools and/or VLSI design). Expenses will be paid by my research grants.
(I hope this will make you get some knowledge about industrial
VLSI CAD tools and design flow.)
- Satisfactory thesis.
Ph.D. Program Requirements
- On-campus course requirements: (1) VLSI Physical Design,
(2) Algorithms, (3) CAD Flow (core course of GIEE), (4) VLSI Design,
(5) Two more courses on VLSI related topics (e.g., VLSI testing, simulation,
logic synthesis, formal verification, advanced VLSI design,
etc),
(6) One more course on mathematics or optimization theory, e.g.,
graph algorithms, combinatorial/discrete optimization, numerical methods,
linear and nonlinear programming, computational geometry, or operations research,
(7) English technical writing (finish this course in the
first year).
(I hope this can solidify your VLSI software as well as hardware
training.)
- Off-campus course requirements (if not taken before):
Selected training courses
offered at CIC (Chip Implementation Center) in Hsinchu
during winter or summer breaks (for learning commercial CAD
tools and/or VLSI design). Expenses will be paid by my research grants.
(I hope this will make you get some knowledge about industrial
VLSI CAD tools and design flow.)
- Satisfactory dissertation (typically formed by at least four conference or journal papers).
- ATTENTION: Don't expect any easy publications.
Should have ACM or IEEE international conference and/or journal
publications to graduate.
(As you can see from our publication page, we publish papers mainly
in IEEE Trans. on CAD,
ACM/IEEE DAC, IEEE/ACM ICCAD, ACM ISPD, ACM/IEEE ASP-DAC, ACM/IEEE DATE,
ACM/IEEE ISLPED, and
IEEE ICCD.)
Paper quality, instead of paper count, is the main criterion
to evaluate whether you can graduate from this group.
(Most Ph.D. graduates from our lab had
ACM/IEEE conference/journal papers sufficient for the
Ph.D. graduation requirements of the Department
in their very first two years, and it took them about
4 years to graduate.)
Note that insignificant publications
will just hurt your academic reputation/career.