Digital Circuits and Systems Laboratory
National Taiwan University

PhD Students

Yu-Chi Lee
李諭奇

Chung-Hsuan Yang
楊仲萱

Yu-Hsuan Tsai
蔡宇軒

Yu-Chen Lo
羅宇呈

Yu-Cheng Lin
林祐丞

Liang-Hsin Lin
林亮昕

Yueh-Feng Tsai
蔡岳峰

Brian Soon Dean
孫振庭

Po-Jen Chen
陳柏任

Chieh-Li Wang
王傑立

MS Students

Chen-Lin Chuang
莊承霖

Jeng-Bang Wang
王政邦

Ren-Hao Chiou
邱仁皓

Xing-Hong Ye
葉星宏

Yao-Kai Yang
楊耀凱

Chun-Hao Chang
張均豪

Minh Khoa Tran
Minh Khoa Tran

Yi-Fan Shyu
徐以帆

Cheng-En Chiang
江承恩

Yi-Chun Liao
廖苡鈞

Chia-Ying Huang
黃佳穎

Can-Lin Wu
吳璨霖

Tzu-Ming Yen
顏子茗

Po-Hao Tseng
曾柏豪

Pre-MS Students

Wei-Chung Chen
陳威仲

Heng-Siang Gao
高珩翔

Yen-Sheng Chiu
邱巖盛

Yi-Cheng Chao
趙翊程

Yu-Hsiang Tsai
蔡宇翔

Ho-Mu Chang
張禾牧

Ching-Ting Hung
洪敬珽

Alumni

Year Degree Name Thesis Affiliation
2025 MS 李其祐 Design and Implementation of a Transformer Learning Processor with Zeroth-Order Optimization Mediatek
2025 MS 李晴妍 An Energy-Efficient Tensor Display Processor for 3D Virtual Reality Mediatek
2025 MS 陳柏任 A High-Throughput Massive MIMO Detector for Rate-Splitting Multiple Access Communication Systems NTU, PhD
2025 MS 陳泰融 An Energy-Efficient Video Inpainting Processor for Real-Time XR Content Creation Mediatek
2025 MS 周子皓 Design and Implementation of Visual-Inertial SLAM Processor for Extended Reality Devices Mediatek
2025 MS 張力元 An Energy-Efficient Hidden-Neural-Network Processor for AIoT-Based Sound Sensing Mediatek
2025 MS 張惇宥 An Energy-Efficient Neural Signal Processor in Speech Decoding for Brain-Machine Interface (Stanford University, PhD)
2024 PhD 駱奕霖 Design and Implementation of a Low-Power Ultrasound Imaging Processor Supporting Standard and Advanced Modes for Hand-Held Devices Mediatek
2024 PhD 陳彥龍 Design and Implementation of Hierarchical Bloom Filter and Dynamic Programming Array for NGS Data Analysis NTU, Postdoc
2024 MS 林瑩昇 Design and Implementation of an Energy Efficient Image Signal Processor for True Video Super-Resolution Mediatek
2024 MS 吳秉陞 An Energy-Efficient Learning Processor for Transformer-Based Neural Networks TSMC
2024 MS 朱怡蓁 A Fully-Integrated Digital Annealing Processor for Large-Scale Autonomous Navigation Optimization Mediatek
2024 MS 張峻瑋 Design and Implementation of a Scene Graph Generation Processor for Visual Context Understanding Mediatek
2024 MS 陳世豪 An Energy-Efficient Neural Network Processor for Reinforcement Learning Realtek
2023 MS 劉宜軒 A Scalable Reconfigurable Deep Learning SoC for Large-Scale Neural Networks Mediatek
2023 MS 陳定揚 An Energy-Aware Deep Learning Accelerator Supporting Dynamic Neural Networks Novatek
2023 MS 李唐 A High-Throughput Massive MU-MIMO Detector for Orthogonal Time Frequency Space Communication Systems Mediatek
2023 PhD 謝伊妍 Design and Implementation of an Energy-Efficient Neural Signal Processor with Adaptable Intelligence for Seizure Prediction Mediatek
2023 MS 杜承諺 Design and Implementation of a Hardware-Utilization-Aware Neural Network Accelerator with Dynamic Dataflow Mediatek
2023 MS 林奕廷 Design and Implementation of a Motion-Control SoC for Autonomous Mobile Robots UC Berkeley, PhD
2023 MS 林禹丞 A High-Throughput Constructive Interference Precoder for MU-MIMO Systems Synopsys
2022 MS 董子維 An SVM Learning Accelerator with a Reconfigurable Computing Array for Neural Signal Processing Mediatek
2022 MS 高禎謙 Design and Implementation of Hybrid Precoding Processor for mmWave Massive MIMO Systems University of Michigan, PhD
2022 MS 傅子興 An Energy-Efficient DNN Processor Supporting Sparsity Scaling for On-Device Training MIT, PhD
2022 MS 黃文璁 Design and Implementation of a CNN-GCN Deep Learning SoC for Mobile Augmented Reality Mediatek
2021 PhD 吳易忠 Design and Implementation of Hardware Accelerators for Next-Generation Sequencing Data Analysis NYCU, Faculty
2021 MS 陳柏劭 An Energy-Efficient Accelerator IC for Dark Channel Prior Based Blind Image Deblurring University of Michigan, PhD
2020 MS 林邑政 Design and Implementation of a Bidirectional RNN FPGA Accelerator for Speech Recognition Mediatek
2020 MS 沈雪巖 Design and Implementation of a Machine-Learning Based Full HD Super-Resolution Accelerator Mediatek
2019 MS 鍾杰 Design and Implementation of a Path Planning Processor for Autonomous Navigation of Micro Robots Mediatek
2019 MS 文及志 A High-throughput Massive MU-MIMO Detector for Next-generation Cellular Systems Mediatek
2019 MS 呂丞勛 A Fully-Programmable Deep Learning Processor with Adaptable Intelligence University of Michigan, PhD
2019 MS 王耀斌 Design of an Iterative Receiver with a Lattice-Reduction-Aided MIMO Detector for IEEE 802.11ax Mediatek
2018 MS 陳彥龍 Design and Implementation of a System-on-Chip for NGS Data Analysis NTU, PhD
2018 MS 王于哲 A Reconfigurable Processor for Reconstruction of Compressively-Sensed Physiological Signals Google
2018 MS 簡全佑 Design and Implementation of a Fast-Locking, Low-Jitter Fractional-N All-digital Phase-Locked Loop Sitronix
2018 MS 蘇郁傑 Design and Implementation of an Iterative Detection and Decoding Receiver for LDPC-coded SCMA Systems Mediatek
2018 MS 葉淳育 A Scalable DSP Architecture for Beam Selection in mm-Wave MU-MIMO Systems Realtek
2018 MS 李諭奇 An Acoustic DSP Processor with Reconfigurable CNN/FFT Accelerators for Speech Enhancement NTU, PhD
2017 MS 黃碩安 A Machine-Learning Processor with On-Chip Active Learning for Closed-Loop Neuromodulation Systems Mediatek
2017 MS 江芷瑄 A Flexible GGMD Processor for MIMO Communication Systems Phison
2016 MS 陳彥同 An Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MIMO Systems Mediatek
2016 MS 楊智文 Design Methodology for Heterogeneous TFET-MOSFET Structure Based Asynchronous FPGA Mediatek
2016 MS 吳易忠 Design and Implementation of a High-Speed Data Processor for Next-Generation Sequencing NTU, PhD
2015 MS 洪若翰 Design of Digital Logic and Asynchronous Datapath with Heterogeneous TFET-MOSFET Structure for Ultralow-Energy Electronics TSMC
2015 MS 林詠仁 Design and Implementation of Acoustic Signal Processor with Spectral Change Enhancement for Cochlear Implants Mediatek
2015 MS 林欣慈 Integration of Energy-Recycling Logic and Wireless Power Transfer for Ultralow-Power Biomedical Implants Ambarella
2014 MS 羅其偉 An Ultra-Low Voltage Error-Resilient FIR Filter Mediatek
2014 MS 周俊瑋 A Systolic Array Based GTD Processor with a Parallel Algorithm Mediatek
2014 MS 蔡雨澄 A Flexible Geometric Mean Decomposition Processor for MIMO Communication Systems NVIDIA
2014 MS 李承晏 Design and Implementation of a Standard-Cell Design Flow Compatible Energy Recycling Logic Ambarella
2014 MS 劉浩皿 Design and Implementation of a Low-Power Acoustic Signal Processor for Bone-Guided Cochlear Prosthesis Academia Sinica