Digital Circuits and Systems Laboratory
National Taiwan University

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Journal Papers

2025

  • J.-F. Wu , T.-H. Chou, P.-H. Tseng, I-J. Tsai, H.-C. Lee, Y.-K. Yang, C.-H. Yang, "Short and Endurance Squeeze Contractile Integral in High-Resolution Anorectal Manometry is Correlated with Vaizey Incontinence Score – A Pilot Study," Journal of Gastroenterology and Hepatology, accepted.
  • Y.-C. Wu, Y.-L. Chen, C.-H. Yang, C.-H. Lee, W.-C. Chen, L.-Y. Lin, N.-S. Chang, C.-P. Lin, C.-S. Chen, J.-H. Hung, and C.-H. Yang, "A 28nm Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing," IEEE Trans. Biomedical Circuits & Systems (TBioCAS), accepted.
  • T. Lee, T.-Y. Chen, I-H. Liu, and C.-H. Yang, "A 40-nm 131mW 6.4Gbps 256×32 Multi-User MIMO OTFS Detector for Next-Gen Communication Systems," IEEE J. Solid-State Circuits (JSSC), accepted.
  • I-T. Lin, Z.-S. Fu, W.-C. Chen, L.-Y. Lin, N.-S. Chang, C.-P. Lin, C.-S. Chen, and C.-H. Yang, "A 28nm 142mW Motion-Control SoC for Autonomous Mobile Robots," IEEE J. Solid-State Circuits (JSSC), accepted.
  • L.-Y. Chen, M. Kao, S.-H. Chen, and C.-H. Yang, “A Diffusionmodel-Based Methodology for Virtual Silicon Data Generation,” IEEE Trans. Electron Devices (TED) Joint Special Issue on Semiconductor Design for Manufacturing, vol. 72, no. 5, pp. 2138–2145, May 2025.
  • L.-Y. Chen, M. Kao, S.-H. Chen, and C.-H. Yang, "A Diffusion-Model-Based Methodology for Virtual Silicon Data Generation," IEEE Trans Semiconductor Manufacturing (T-SM), vol. 38, no. 2, pp. 146-153, May 2025.
  • Y.-C. Lo, Y.-C. Wu, and C.-H. Yang, "A 44.3mW 62.4fps Hyperspectral Image Processor for Spectral Unmixing in MAV Remote Sensing," IEEE J. Solid-State Circuits (JSSC), vol. 60, no. 5, pp. 1818-1829, May 2025.
  • Y.-L. Lo, Y.-C. Lo, and C.-H. Yang, "A 40-nm 169mW Ultrasound Imaging Processor Supporting Advanced Modes for Hand-Held Devices," IEEE Trans. Biomedical Circuits & Systems (TBioCAS), vol. 19, no. 2, pp. 428-441, Apr. 2025.

2024

  • Y.-H. Tsai, Y.-C. Lin, W.-C. Chen, L.-Y. Lin, N.-S. Chang, C.-P. Lin, S.-H. Chen, C.-S. Chen, C.-H. Yang, "A 28-nm 1.3-mW Speech-to-Text Accelerator for Edge AI Devices," IEEE J. Solid-State Circuits (JSSC), vol. 59, no. 11, pp. 3816-3826, Nov. 2024.
  • W.-C. Huang, I.-T. Lin, Y.-S. Lin, W.-C. Chen, L.-Y. Lin, N.-S. Chang, C.-P. Lin, C.-S. Chen, and C.-H. Yang, "A 25.1-TOPS/W Sparsity-Aware Hybrid CNN-GCN Deep Learning SoC for Mobile Augmented Reality," IEEE J. Solid-State Circuits (JSSC), vol. 59, no. 11, pp. 3840-3852, Nov. 2024.
  • T.-W. Tong, T.-J. Chen, Y.-Y. Hsieh, and C.-H. Yang, "A 73.8K inference/mJ SVM Learning Accelerator for Brain Pattern Recognition," IEEE J. Solid-State Circuits (JSSC) A-SSCC Special Issue, vol. 59, no. 10, pp. 3357-3365, Oct. 2024.
  • Y.-C. Lin, R.-H. Chiou, and C.-H. Yang, "A High-Throughput Constructive Interference Precoder for 16×16 MU-MIMO Systems," IEEE Trans. Very Large Scale Integration (TVLSI), vol. 32, no. 10, pp. 1878 - 1888, July 2024.
  • P.-S. Chen, Y.-L. Chen, Y.-C. Lee, Z.-S. Fu, C.-H. Yang, "A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring," IEEE J. Solid-State Circuits (JSSC), vol. 59, no. 6, pp. 1899-1911, June 2024.
  • J.-F. Wu, Y.-C. Lin, C.-H. Yang, P.-H. Tseng, I.-J. Tsai, W.-H. Lin, W.-M. Hsu, "Clinical Utility of Anal Sphincter Relaxation Integral in Water-perfused and Solid-state High-resolution Anorectal Manometry," Journal of the Formosan Medical Association, 123(2), pp.267-272, Feb. 2024.

2023

  • C.-H. Yang, Y.-C. Wu, Y.-L. Chen, C.-H. Lee, J.-H. Hung, and C.-H. Yang, "An FM-index Based High-Throughput Memory-Efficient FPGA Accelerator for Paired-end Short-read Mapping," IEEE Trans. Biomedical Circuits & Systems (TBioCAS), vol. 17, no. 6, pp. 1331-1341, Dec. 2023.
  • S.-J. Yu, Y.-C. Lee, L.-H. Lin, and C.-H. Yang, "An Energy-efficient Double Ratchet Cryptographic Processor with Backward Secrecy for IoT Devices," IEEE J. Solid-State Circuits (JSSC), vol. 58, no. 6, pp. 1810-1819, June 2023.
  • H.-Y. Shen, Y.-C. Lee, Z.-W. Tong, and C.-H. Yang, "A 40-nm 91-mW, 90-fps Learning-Based Full HD Super-Resolution Accelerator," IEEE J. Solid-State Circuits (JSSC), vol. 58, no. 2, pp. 520-529, Feb. 2023.
  • Y.-Y. Hsieh, Y.-C. Lin, and C.-H. Yang, "A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction," IEEE J. Solid-State Circuits (JSSC), vol. 58, no. 1, pp. 167-176, Jan. 2023.

2022

  • Y.-S. Lin, Y.-P. Wu, Y.-C. Wu, P.-L. Lee, and C.-H. Yang, "Achieving Accurate Automatic Sleep Apnea/Hypopnea Syndrome Assessment Using Nasal Pressure Signal," IEEE Journal of Biomedical and Health Informatics (JBHI), vol. 26, no. 11, pp. 5473-5481, Nov. 2022.
  • C.-C. Kao, C.-E. Chen, C.-H. Yang, "Hybrid Precoding Baseband Processor for 64x64 Millimeter Wave MIMO Systems," IEEE Trans. Circuits & Systems I (TCAS-I), vol. 69, no. 4, pp. 1765-1773, April 2022.

2021

  • J.-F. Wu, W.-C. Hsu, I.-J. Tsai, T.-W. Tong, Y.-C. Lin, C.-H. Yang, and P.-H. Tseng, "Bolus transit of upper esophageal sphincter on high-resolution impedance manometry study correlate with the laryngopharyngeal reflux symptoms," Scientific Reports, 11(1), pp.1-9, Oct. 2021.
  • S.-H. Wang, Y.-K. Huang, C.-Y. Chen, L.-Y. Tang, Y.-F. Tu, P.-C. Chang, C.-F. Lee, C.-H. Yang, C.-C. Hung, C.-H. Liu, M.-D. Ker, and C.-Y. Wu, "Design of a Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Evoked Compound Action Potential Acquisition and Its In Vivo Verification," IEEE J. Solid-State Circuits (JSSC) A-SSCC 2020 Special Issue, vol. 56, no. 10, pp. 3062-3076, Oct. 2021.
  • Y.-L. Chen, B.-Y. Chang, C.-H. Yang, and T.-D. Chiueh, "A High-throughput FPGA Accelerator for Short-read Mapping of the Whole Human Genome," IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 32, no. 6, pp. 1465-1478, June 2021.
  • C. Chung and C.-H. Yang, "A 1.5-μJ/Task Path-Planning Processor for 2-D/3-D Autonomous Navigation of Microrobots," IEEE J. Solid-State Circuits (JSSC) ISSCC 2020 Special Issue, vol. 56, no. 1, pp. 112-122, Jan. 2021.
  • Y.-C. Wu, Y.-L. Chen, C.-H. Yang, C.-H. Lee, C.-Y. Yu, N.-S. Chang, L.-C. Chen, J.-R. Chang, C.-P. Lin, H.-L. Chen, C.-S. Chen, J.-H. Hung, and C.-H. Yang, "A 975mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28nm for Next-Generation Sequencing," IEEE J. Solid-State Circuits (JSSC) ISSCC 2020 Special Issue, vol. 56, no. 1, pp. 123-135, Jan. 2021.

2020

  • J.-H. Hung, P.-Y. Wang, Y.-C. Lo, C.-W. Yang, B.-Y. Tsui, and C.-H. Yang, "Digital Logic and Asynchronous Datapath with Heterogeneous TFET-MOSFET Structure for Ultralow-Energy Electronics," IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), vol. 6, no. 2, Dec. 2020.
  • Y.-J. Lin, Y.-C. Lee, H.-M. Liu, H. Chiueh, T.-S. Chi, and C.-H. Yang, "A 1.5mW Programmable Acoustic Signal Processor for Hearing Assistive Devices with Speech Intelligibility Enhancement," IEEE Trans. Circuits & Systems I (TCAS-I), vol. 67, no. 12, pp. 4984-4993, Dec. 2020.
  • J.-F. Wu, I.-J. Tsai, T.-W. Tong, Y.-C. Lin, C.-H. Yang, and P.-H. Tseng, "Pressure-impedance analysis assisted the diagnosis and classification of ineffective esophageal motility disorder," Journal of Gastroenterology and Hepatology (JGH), vol. 35, no. 8, pp. 1317-1324, July 2020.
  • Y.-C. Lee, T.-S. Chi, and C.-H. Yang, "A 2.17mW Acoustic DSP Processor with CNN-FFT Accelerators for Intelligent Hearing Assistive Devices," IEEE J. Solid-State Circuits (JSSC), vol. 55, no. 8, pp. 2247-2258, Apr. 2020.
  • S.-A. Huang, K.-C. Chang, H.-H. Liou, and C.-H. Yang, "A 1.9mW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control," IEEE J. Solid-State Circuits (JSSC), vol. 55, no. 2, pp. 452-464, Feb. 2020.

2019

  • Y.-Z. Wang, Y.-P. Wang, Y.-C. Wu, C.-H. Yang, "A 12.6mW 573-2,901KS/s Reconfigurable Processor for Reconstruction of Compressively-Sensed Physiological Signals," IEEE J. Solid-State Circuits (JSSC), vol. 54, no. 10, pp. 2907-2916, Oct. 2019.
  • W.-C. Sun, Y.-C. Su, Y.-L. Ueng, C.-H. Yang, "An LDPC-Coded SCMA Receiver with Multi-User Iterative Detection and Decoding," IEEE Trans. Circuits & Systems I (TCAS-I), vol. 66, no. 9, pp. 3571-3584, July 2019.
  • X.-H. Qian, Y.-C. Wu, T.-Y. Yang, C.-H. Cheng, S.-C. Chu, W.-H. Cheng, T.-Y. Yen, T.-H. Lin, Y.-J. Lin, Y.-C. Lee, J.-H. Chang, S.-T. Lin, S.-H. Li, T.-C. Wu, C.-C. Huang, S.-H. Wang, C.-F. Lee, C.-H. Yang, C.-C. Hung, T.-S. Chi, C.-H. Liu, M.-D. Ker, and C.-Y. Wu, "Design and In-Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem," IEEE Transactions on Biomedical Engineering (TBME), vol. 66, no. 11, pp. 3156-3167, Feb. 2019.
  • W.-C. Sun, Y.-T. Chen, C.-H. Yang, and Y.-L. Ueng, "Iterative Inter-cell Interference Cancellation Receiver for LDPC-coded MIMO Systems," IEEE Trans. Signal Processing (TSP), vol. 67, no. 6, pp. 1636-1647, Mar. 2019.
  • Y.-T. Chen, W.-C. Sun, C.-C. Cheng, T.-L. Tsai, Y.-L. Ueng, and C.-H. Yang, "An Integrated Message-Passing Detector and Decoder for Polar-coded Massive MU-MIMO Systems," IEEE Trans. Circuits & Systems I (TCAS-I), vol. 66, no. 3, pp. 1205-1218, Mar. 2019.

2018

  • J.-F. Wu, C. Chung, P.-H. Tseng, I.-J. Tsai, Y.-H. Lin, C.-H. Yang, "Distal contractile to impedance integral ratio assist the diagnosis of pediatric ineffective esophageal motility disorder," Pediatric Research, vol. 84, no. 6, pp. 849-853, Oct. 2018.
  • C.-Y. Yeh, T.-C. Chu, C.-E. Chen, C.-H. Yang, “A Hardware-Scalable DSP Architecture for Beam Selection in mm-Wave MU-MIMO Systems," IEEE Trans. Circuits & Systems I (TCAS-I), vol. 65, no. 11, pp. 3918-3928, Nov. 2018.
  • T.-I Chou, K.-H. Chang, J.-Y. Jhang, S.-W. Chiu, G. Wang, C.-H. Yang, H. Chiueh, H. Chen, C.-C. Hsieh, M.-F. Chang, K.-T. Tang, “A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip," IEEE Trans. Circuits & Systems II (TCAS-II), vol. 65, no. 10, pp. 365-1369, July 2018.
  • J.-F. Wu, C.-H. Lu, C.-H. Yang, I.-J. Tsai, “Diagnostic Role of Anal Sphincter Relaxation Integral (ASRI) in High-resolution Anorectal Manometry for Hirschsprung's Disease in Infants,” Journal of Pediatrics, vol. 194, pp. 136-141, Mar. 2018.

2017

  • Y.-C. Wu, J.-H. Hung, C.-H. Yang, “A 135mW Fully Integrated Data Processor for Next-Generation Sequencing,” IEEE Trans. Biomedical Circuits & Systems (TBioCAS) ISSCC 2017 Special Issue, vol. 11, no. 6, pp. 1216-1225, Dec. 2017.
  • M.-R. Li, C.-H. Yang, Y.-L. Ueng, “A 5.28-Gbps LDPC Decoder with Time-domain Signal Processing for IEEE 802.15.3c Applications,” IEEE J. Solid-State Circuits (JSSC), vol. 52, no. 2, pp. 592-604, Feb. 2017.
  • Y.-C. Tsai, C.-E. Chen, C.-H. Yang, “A Flexible Geometric Mean Decomposition Processor for MIMO Communication Systems,” IEEE Trans. Circuits & Systems I (TCAS-I), vol. 64, no. 2, pp. 446-456, Feb. 2017.

2016

  • C.-H. Chang, M.-T. Chou, Y.-C. Wu, T.-W. Hong, Y.-L. Li, C.-H. Yang, and J.-H. Hung, “sBWT: Memory Efficient Implementation of the Hardware-acceleration-friendly Schindler Transform for the Fast Biological Sequence Mapping,” Bioinformatics 32.22, pp. 3498-3500, July 2016.
  • C.-Y. Lee, P.-H. Hsieh, and C.-H. Yang, “A Standard-Cell-Design-Flow Compatible Energy-Recycling Logic with 70% Energy Saving,” IEEE Trans. Circuits & Systems I (TCAS-I), vol. 63, no. 1, pp. 70-79, Jan. 2016.

2015

  • W.-H. Wu, W.-C. Sun, C.-H. Yang, and Y.-L. Ueng, “An Iterative Detection and Decoding Receiver for LDPC-Coded MIMO Systems,” IEEE Trans. Circuits & Systems I (TCAS-I), vol. 62, no. 10, pp. 212-2522, Oct. 2015.
  • C.-H. Yang, C.-W. Chou, C.-S. Hsu, C.-E. Chen, “A Systolic Array Based GTD Processor with a Parallel Algorithm,” IEEE Trans. Circuits & Systems I (TCAS-I), vol. 62, no. 4, pp. 1099-1108, April 2015.
  • C.-E. Chen, Y.-C. Tsai, and C.-H. Yang, “An Iterative Geometric Mean Decomposition Algorithm for MIMO Communications Systems,” IEEE Trans. Wireless Communications (TWC), vol. 14, no. 1, pp.343-352, Jan. 2015.
  • C.-H. Yang, Y.-H. Shih, and H. Chiueh, “An 81.6μW FastICA Processor for Epileptic Seizure Detection,” IEEE Trans. Biomedical Circuits & Systems (TBioCAS), vol. 9, no.1, pp. 60-71, Feb. 2015.

2014

  • S.-W. Chiu, J.-H. Wang, K.-H. Chang, T.-H. Chang, C.-M. Wang, C.-L. Chang, C.-T. Tang, C.-F. Chen, C.-H. Shih, H.-W. Kuo, L.-C. Wang, H. Chen, C.-C. Hsieh, M.-F. Chang, Y.-W. Liu, T.-J. Chen, C.-H. Yang, H. Chiueh, J.-M. Shyu, K.-T. Tang, “A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia,” IEEE Trans. Biomedical Circuits & Systems (TBioCAS), vol. 8, no. 6, pp. 765-778, Dec. 2014.
  • C.-H. Yang, T.-Y. Huang, M.-R. Li, and Y.-L. Ueng, “A 5.4μW Soft-Decision BCH Decoder for Wireless Body Area Networks,” IEEE Trans. Circuits & Systems I (TCAS-I), vol. 61, no. 9, pp. 2721-2729, Sep. 2014.
  • C.-C. Cheng, J.-D. Yang, C.-H. Yang, and Y.-L. Ueng, “A Fully-Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications,” IEEE Trans. Circuits & Systems I (TCAS-I), vol. 61, no. 9, pp. 2738-2746, Sep. 2014.
  • W.-M. Chen, H. Chiueh, T.-J. Chen, C.-L. Ho, C. Jeng, S.-T. Chang, M.-D. Ker, C.-Y. Lin, Y.-C. Huang, C.-W. Chou, T.-Y. Fan, M.-S. Cheng, S.-F. Liang, T.-C. Chien, S.-Y. Wu, Y.-L. Wang, F.-Z. Shaw, Y.-H. Huang, C.-H. Yang, C.-Y. Wu, “A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic SoC for Real-Time Epileptic Seizure Control,” IEEE J. Solid-State Circuits (JSSC), vol. 49, no. 1, pp. 232-247, Jan. 2014.

2013

  • S.-F. Liang, Y.-C. Chen, Y.-L. Wang, P.-T. Chen, C.-H. Yang, and H. Chiueh, "A Hierarchical Approach for On-line Temporal Lobe Seizure Detection in Long-term Intracranial EEG Recordings," J. Neural Engineering (JNE), NIC special issue, vol. 10, no. 4, pp. 1-14, May, 2013.

2012

  • T.-H. Yu, C.-H. Yang, D. Čabrić, and D. Marković, "A 7.4 mW 200 MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios," IEEE J. Solid-State Circuits (JSSC), vol. 47, no. 9, pp. 2235-2245, Sept. 2012.
  • C.-H. Yang, T.-H. Yu, and D. Marković, "Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example," IEEE J. Solid-State Circuits (JSSC), vol. 47, no. 3, pp. 757-767, Mar. 2012.

2009 - 2011

  • C.-H. Yang and D. Marković, "A Flexible DSP Architecture for MIMO Sphere Decoding," IEEE Trans. Circuits & Systems I (TCAS-I), vol. 56, no. 10, pp. 2301-2314, Oct. 2009.

Conference Papers

2025

  • Y.-C. Lin, M.-S. Huang, J.-B. Wang, W.-C. Chen, N.-S. Chang, C.-P. Lin, C.-S. Chen, T.-D. Chiueh, and C.-H. Yang, "A 16nm Fully Integrated SoC for Hardware-Aware Neural Architecture Search," 2025 European Solid-State Electronics Research Conference (ESSERC), accepted
  • P.-J. Chen, R.-H. Chiou, C.-H. Yang, "A 142mW 6.4Gbps Massive MU-MIMO RSMA Detector for Next-Generation Communication Systems," Int. Symposium on VLSI Circuits (VLSI Circuits), June 2025.
  • C.-Y. Li, Y.-F. Shyu, and C.-H. Yang, "An 157TOPS/W Transformer Learning Processor Supporting Forward Pass Only with Zeroth-Order Optimization," Int. Symposium on VLSI Circuits (VLSI Circuits), June 2025.
  • S.-H. Chen, P.-S. Wu, B. D. Soon, C.-H. Chen, C.-W. Liu, C.-L. Hsu, and C.-H. Yang, "A 209TOPS/W Reinforcement Learning Processor with Full Speculation Exploitation and Inference-Training Parallel Processing," IEEE Custom Integrated Circuits Conference (CICC), Apr. 2025. (Best Paper Finalist)
  • Y.-S. Lin, J. Nishimura, C.-H. Yang, "A 210fps Image Signal Processor for 4K Ultra HD True Video Super-Resolution," Int. Solid-State Circuits Conference (ISSCC), pp. 58-59, Feb. 2025.
  • L.-H. Lin, Y.-K. Yang, C.-H. Yang, "A 30.4GOPS/mW MK-CKKS Processor for Secure Multi-party Computation," Int. Solid-State Circuits Conference (ISSCC), pp. 296-297, Feb. 2025.
  • T.-Y. Chang, J.-B. Wang, Y.-H. Tsai, C.-H. Yang, "A 3.9mW, 200words/min Neural Signal Processor in Speech Decoding for Brain-Machine Interface," Int. Solid-State Circuits Conference (ISSCC), pp. 266-267, Feb. 2025.

2024

  • T.-Y. Chen, Y.-L. Lo, T.-Y. Chang, and C.-H. Yang, "An 8.1-to-353 TOPS/W Energy-Aware Deep-Learning Accelerator Supporting Dynamic Neural Networks," IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2024.
  • I.-H. Liu, I.-T. Lin, Y.-F. Tsai, J.-S. Hsieh, V. Chen, C.-T. Wang, C.-H. Yang, and D. C.H. Yu, "A 28-nm 141.4TOPS/W Scalable Reconfigurable Deep Learning SoC for Large-Scale Neural Networks," 2024 IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2024.
  • C.-W. Chang, I.-T. Lin, C.-H. Yang, "A 101mW, 280fps Scene Graph Generation Processor for Visual Context Understanding on Mobile Devices," Int. Symposium on VLSI Circuits (VLSI Circuits), June 2024.
  • P.-S. Wu, Y.-C. Lin, C.-H. Yang, "A 99.2TOPS/W Transformer Learning Processor with Approximated Attention Score Gradient Computation and Ternary Vector-based Speculation," Int. Symposium on VLSI Circuits (VLSI Circuits), June 2024.
  • Y.-C. Lin, R.-H. Chiou, Y.-C. Lin, and C.-H. Yang, "A 919GMACs/J Reconfigurable SIMD Array Processor for Baseband Signal Processing," Int. VLSI Symposium on Technology, Systems and Applications (VLSI TSA), Apr. 2024.
  • Y.-C. Chu, Y.-C. Lin, Y.-C. Lo, C.-H. Yang, "Fully Integrated Annealing Processor for Large-Scale Autonomous Navigation Optimization," Int. Solid-State Circuits Conference (ISSCC), pp. 46-47, Feb. 2024.
  • T. Lee, T.-Y. Chen, I.-H. Liu, and C.-H. Yang, "A 131mW 6.4Gbps 256×32 Multi-User MIMO OTFS Detector for Next-Gen Communication Systems," Int. Solid-State Circuits Conference (ISSCC), pp. 488-489, Feb. 2024.

2023

  • T.-W. Tong, Y.-Y. Hsieh, T.-J. Chen, C.-H. Yang, "A 73.8K inference/mJ SVM Learning Accelerator for Brain Pattern Recognition," IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2023.
  • Y.-C. Lin, C. Park, W. Zhao, N. Sun, Y. Chae, and C.-H. Yang, "A 26.4mW, 18.6MS/s Image Reconstruction Processor for IoT Compressive Sensing," Int. Symposium on VLSI Circuits (VLSI Circuits), June 2023.
  • Y.-L. Lo, Y.-C. Lo and C.-H. Yang, "A 169mW Fully-Integrated Ultrasound Imaging Processor Supporting Advanced Modes for Hand-Held Devices," Int. Symposium on VLSI Circuits (VLSI Circuits), June 2023.
  • L.-H. Lin, Z.-S. Fu, P.-S. Chen, B.-Y. Yang, and C.-H. Yang, "A 4.8mW, 800Mbps Hybrid Crypto SoC for Post-Quantum Secure Neural Interfacing," Int. Symposium on VLSI Circuits (VLSI Circuits), June 2023.
  • Y.-L. Chen, C.-H. Yang, Y.-C. Wu, C.-H. Lee, W.-C. Chen, L.-Y. Lin, N.-S. Chang, C.-P. Lin, C.-S. Chen, J.-H. Hung, C.-H. Yang, "A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing," Int. Solid-State Circuits Conference (ISSCC), pp. 44-45, Feb. 2023.
  • I.-T. Lin, Z.-S. Fu, W.-C. Chen, L.-Y. Lin, N.-S. Chang, C.-P. Lin, C.-S. Chen, C.-H. Yang, "A 28nm 142mW Motion-Control SoC for Autonomous Mobile Robots," Int. Solid-State Circuits Conference (ISSCC), pp. 46-47, Feb. 2023.
  • C.-Y. Du, C.-F. Tsai, W.-C. Chen, L.-Y. Lin, N.-S. Chang, C.-P. Lin, C.-S. Chen, C.-H. Yang, "A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow," Int. Solid-State Circuits Conference (ISSCC), pp. 332-333, Feb. 2023.

2022

  • Y.-H. Tsai, Y.-C. Lin, W.-C. Chen, L.-Y. Lin, N.-S. Chang, C.-P. Lin, S.-H. Chen, C.-S. Chen, C.-H. Yang, "A 1.3mW Speech-to-Text Accelerator with Bidirectional Light Gated Recurrent Units for Edge AI," IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2022.
  • C.-H. Yang, Y.-C. Wu, Y.-L. Chen, C.-H. Lee, J.-H. Hung, C.-H. Yang, "A 75.6M Base-pairs/s FPGA Accelerator for FM-index Based Paired-end Short-Read Mapping," IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2022.
  • C.-C. Kao, Y.-Y Hsieh, C.-H. Chen, and C.-H. Yang, "Hardware Acceleration in Large-Scale Tensor Decomposition for Neural Network Compression," Int. Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2022.
  • Z.-S. Fu, Y.-C. Lee, A. Park, C.-H. Yang, “A 40-nm 646.6TOPS/W Sparsity-Scaling DNN Processor for On-Device Training,” Int. Symposium on VLSI Circuits (VLSI Circuits), pp. 40-41, June 2022.
  • W.-C. Huang, I.-T. Lin, W.-C. Chen, L.-Y. Lin, N.-S. Chang, C.-P. Lin, C.-S. Chen, C.-H. Yang, "A 28-nm 25.1 TOPS/W Sparsity-Aware CNN-GCN Deep Learning SoC for Mobile Augmented Reality," Int. Symposium on VLSI Circuits (VLSI Circuits), pp. 42-43, June 2022.
  • Y.-C. Lo, Y.-C. Wu, C.-H. Yang, "A 44.3mW 62.4fps Hyperspectral Image Processor for MAV Remote Sensing," Int. Symposium on VLSI Circuits (VLSI Circuits), pp. 74-75, June 2022.
  • Y.-Y. Hsieh, Y.-C. Lin, C.-H. Yang, "A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction," Int. Solid-State Circuits Conference (ISSCC), pp. 506-508, Feb. 2022.

2021

  • S.-J. Yu, Y.-C. Lee, and C.-H Yang, "A 1.18mW Double Ratchet Cryptographic Processor with Backward Secrecy for IoT Devices," IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2021.
  • P.-S. Chen, Y.-L. Chen, Y.-C. Lee, Z.-S. Fu, C.-H. Yang, "A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring," IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2021.
  • S.-A. Huang, Y.-Y. Hsieh, and C.-H. Yang, "Design Optimization for ADMM-Based SVM Training Processor for Edge Computing," Proc. Int. Conference on Artificial Intelligence Circuits and Systems (AICAS), June 2021.
  • Y.-L. Lo and C.-H. Yang, "A Color Doppler Processing Engine with An Adaptive Clutter Filter for Portable Ultrasound Imaging Devices," Proc. Int. Conf. Acoustics, Speech and Signal Processing (ICASSP), June 2021.
  • H.-Y. Shen, Y.-C. Lee, T.-W. Tong, and C.-H. Yang, "A 91mW 90fps Super-Resolution Processor for Full HD Images," Int. Solid-State Circuits Conference (ISSCC), pp. 66-67, Feb. 2021.

2020

  • Y.-P. Wang, C.-C. Wen, C.-C. Kao, C.-J. Huang, D.-Z. Liu, and C.-H. Yang, "Iterative Receiver with a Lattice-Reduction-Aided MIMO Detector for IEEE 802.11ax," Global Communications Conference (GLOBECOM), Dec. 2020.
  • S.-H. Wang, Y.-K. Huang, C.-Y. Chen, C.-F. Lee, C.-H. Yang, C.-C. Hung, C.-H. Liu, M.-D. Ker, and C.-Y. Wu, "Improved Design and in Vivo Animal Tests of Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Neural Action Potential Acquisition," IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2020.
  • Y.-Y. Hsieh, Y.-C. Lee, C.-H. Yang, "A CycleGAN Accelerator for Unsupervised Learning on Mobile Devices," Int. Symposium Circuits and Systems (ISCAS), Oct. 2020.
  • Y.-C. Wu, Y.-L. Chen, C.-H. Yang, C.-H. Lee, C.-Y. Yu, N.-S. Chang, L.-C. Chen, J.-R. Chang, C.-P. Lin, H.-L. Chen, C.-S. Chen, J.-H. Hung, C.-H. Yang, "A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing," Hot Chips 2020, Aug. 2020.
  • H. Chiueh, C.-H. Yang, C. H.-P. Wen, C.-G. Yang, P.-H. Chien, C.-Y. Hung, Y.-J. Chen, Y.-P. Wang, C.-F. Chiu, J. Lin, "Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS," Int. Symposium VLSI Design, Automation & Test (VLSI-DAT), Aug. 2020.
  • C.-C. Wen, Y.-C. Lee, Y.-C. Wu, C.-C. Kao, C.-H. Yang, "A 1.96 Gb/s Massive MU-MIMO Detector for Next-Generation Cellular Systems," Int. Symposium on VLSI Circuits (VLSI Circuits), June 2020.
  • Y.-C. Wu, Y.-L. Chen, C.-H. Yang, C.-H. Lee, C.-Y. Yu, N.-S. Chang, L.-C. Chen, J.-R. Chang, C.-P. Lin, H.-L. Chen, C.-S. Chen, J.-H. Hung, C.-H. Yang, "A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing," Int. Solid-State Circuits Conference (ISSCC), pp. 322-323, Feb. 2020.
  • C. Chung and C.-H. Yang, "A 1.5μJ/Task Path-Planning Processor for 2D/3D Autonomous Navigation of Micro Robots," Int. Solid-State Circuits Conference (ISSCC), pp. 324-325, Feb. 2020.

2019

  • C.-H. Lu, Y.-C. Wu, and C.-H. Yang, "A 2.25 TOPS/W Fully-Integrated Deep CNN Learning Processor with On-Chip Training," IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 65-58, Nov. 2019.
  • W.-C. Sun, Y.-C. Su, Y.-L. Ueng, and C.-H. Yang, "An LDPC-Coded SCMA Receiver with Multi-User Iterative Detection and Decoding," IEEE Int. Symposium on Integrated Circuits and Systems (ISICAS), Sep. 2019.
  • Y.-Z. Wang, J. Wu, S.-H. Chen, Mango C.-T. Chao, and C.-H. Yang, “Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs,” Proc. Int. Symposium VLSI Design, Automation & Test (VLSI-DAT), Apr. 2019.
  • W.-C. Huang and C.-H. Yang, "RISC-V Architecture Optimization through Extensible Instruction Sets and Custom Accelerators," RISC-V Workshop, Mar. 2019.
  • Y.-C. Lee, T.-S. Chi, and C.-H. Yang, “A 2.17mW Acoustic DSP Processor with CNN-FFT Accelerators for Intelligent Hearing Aided Devices,” Proc. Int. Conference on Artificial Intelligence Circuits and Systems (AICAS), Mar. 2019.

2018

  • C.-Y. Yeh, T.-C. Chu, C.-E. Chen, C.-H. Yang, “A Hardware-Scalable DSP Architecture for Beam Selection in mm-Wave MU-MIMO Systems," IEEE Int. Symposium on Integrated Circuits and Systems (ISICAS), Sep. 2018.
  • T.-I Chou, K.-H. Chang, J.-Y. Jhang, S.-W. Chiu, G. Wang, C.-H. Yang, H. Chiueh, H. Chen, C.-C. Hsieh, M.-F. Chang, K.-T. Tang, “A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip," IEEE Int. Symposium on Integrated Circuits and Systems (ISICAS), Sep. 2018.
  • S.-A. Huang, K.-C. Chang, H.-H. Liou, and C.-H. Yang, “A 1.9mW SVM Processor with On-chip Active Learning for Epileptic Seizure Control,” Proc. Int. Symposium on VLSI Circuits (VLSI Circuits), pp. 259-260, June 2018.
  • Y.-Z. Wang, Y.-P. Wang, Y.-C. Wu, C.-H. Yang, “A 12.6mW 573-2,901KS/s Reconfigurable Processor for Reconstruction of Compressively-Sensed Physiological Signals,” Proc. Int. Symposium on VLSI Circuits (VLSI Circuits), pp. 261-262, June 2018.
  • C.-H. Chiang, S.-A. Huang, C.-E. Chen, and C.-H. Yang, “A 2x2-16x16 Reconfigurable GGMD Processor for MIMO Communication Systems,” Int. Symposium Circuits and Systems (ISCAS), pp. 1-5, May 2018.

2017

  • Y.-T. Chen, C.-C. Cheng, T.-L. Tsai, W.-C. Sun, Y.-L. Ueng, C.-H. Yang, “A 501mW 7.61Gb/s Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MIMO Systems,” Proc. Int. Symposium on VLSI Circuits (VLSI Circuits), pp. 330-331, June 2017.
  • X.-H. Qian, Y.-C. Wu, T.-Y. Yang, C.-H. Cheng, H.-C. Chu, W.-H. Cheng, T.-Y. Yen,T.-H. Lin, Y.-J. Lin, Y.-C. Lee, J.-H. Chang, S.-T. Lin, S.-H. Li, T.-C. Wu, C.-C. Huang, C.-F. Lee, C.-H. Yang, C.-C. Hung, T.-S. Chi, C.-H. Liu, M.-D. Ker, and C.-Y. Wu, “A Bone-Guided Cochlear Implant CMOS Microsystem Preserving Acoustic Hearing,” Proc. Int. Symposium on VLSI Circuits (VLSI Circuits), pp. 46-47, June 2017.
  • H.-T. Lin, Y.-C. Wu, P.-H. Hsieh, C.-H. Yang, “Integration of Energy-Recycling Logic and Wireless Power Transfer for Ultra-Low-Power Implantables,” Int. Symposium Circuits and Systems (ISCAS), pp. 1-4, May 2017.
  • W.-C. Sun, C.-H. Yang, and Y.-L. Ueng, “An Area-Efficient Multi-Mode LLR Computing Engine for MMSE-Based MIMO Detectors,” IEEE Vehicular Technology Conf. (VTC-Spring), June 2017.
  • Y.-C. Wu, J.-H. Hung, C.-H. Yang, “A 135mW Fully Integrated Data Processor for Next-Generation Sequencing,” Int. Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 252-253, Feb. 2017.

2016

  • T.-I. Chou, S.-W. Chiu, K.-H. Chang, Y.-J. Chen, C.-T. Tang, C.-H. Shih, C.-C. Hsieh, M.-F. Chang, C.-H. Yang, H. Chiueh, and K.-T. Tang, “Design of a 0.5V 1.68mW Nose-on-a-Chip for Rapid Screen of Chronic Obstructive Pulmonary Disease,” IEEE Biomedical Circuits & Systems Conf. (BioCAS), pp. 592-595, Nov. 2016.
  • H.-M. Liu, Y.-J. Lin, Y.-C. Lee, C.-Y. Lee, C.-H. Yang, “A 98μW Auditory DSP Processor for Cochlear Implants,” Int. Symposium VLSI Design, Automation & Test (VLSI-DAT), pp. 1-4, Apr. 2016. (Best Paper Award Nomination)
  • W.-C. Liu, C.-D. Chan, S.-A. Huang, C.-W. Lo, C.-H. Yang, S.-J. Jou, “Error-Resilient Sequential Cells with Successive Time Borrowing for Stochastic Computing,” Proc. Int. Conf. Acoustics, Speech and Signal Processing (ICASSP), pp. 6545-6549, Mar. 2016.

2015

  • J.-H. Hung, P.-Y. Wang, B.-Y. Tsui, C.-H. Yang, “A Concept of Heterogeneous Circuits with Epitaxial Tunnel Layer Tunnel FETs,” Proc. International Conference on Solid State Devices and Materials (SSDM), Sep. 2015.
  • W.-H. Wu, W.-C. Sun, C.-H. Yang, and Y.-L. Ueng, “A 794Mbps 135mW Iterative Detection and Decoding Receiver for LDPC-Coded MIMO Systems,” Proc. Int. Symposium on VLSI Circuits (VLSI Circuits), pp. 102-103, June 2015.

2014

  • C.-H. Yang, Y.-H. Shih, and H. Chiueh, “A FastICA Processor for Epileptic Seizure Detection and Brain-Machine Interfaces,” in IEEE EMBS BRAIN Grand Challenges Conference, Nov. 2014.
  • K.-T. Tang, S.-W. Chiu, C.-H. Shih, C.-L. Chang, C.-M. Yang, D.-J. Yao, J.-H. Wang, C.-M. Huang, H. Chen, K.-H. Chang, C.-C. Hsieh, T.-H. Chang, M.-F. Chang, C.-M. Wang, Y.-W. Liu, T.-J. Chen, C.-H. Yang, H. Chiueh, J.-M. Shyu, “A 0.5V 1.27mW Nose-on-a-Chip for Rapid Diagnosis of Ventilator-associated Pneumonia,” Int. Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 420-421, Feb. 2014.

2013

  • T.-J. Chen, S.-C. Lee, C.-H. Yang, C.-F. Chiu, and H. Chiueh, “A 28.6μW Mixed-Signal Processor for Epileptic Seizure Detection,” in Proc. Int. Symposium on VLSI Circuits (VLSI Circuits), pp. 52-53, June 2013.
  • L.-L. Wang, C.-H. Yang, and H. Chiueh, “A 191μW BPSK Demodulator for Data and Power Telemetry in Biomedical Implants,”in Proc. Great Lakes Symposium on VLSI (GLVLSI) , pp. 119-124, May 2013.
  • C.-D. Chan, W.-C. Liu, C.-H. Yang, and S.-J. Jou, “Power and Area Reduction in Multi-Stage Addition Using Operand Segmentation,” in Int. Symposium on VLSI Design, Automation & Test (VLSI-DAT), Apr. 2013.
  • W.-M. Chen, H. Chiueh, T.-J. Chen, C.-L. Ho, C. Jeng, S.-T. Chang, M.-D. Ker, C.-Y. Lin, Y.-C. Huang, C.-W. Chou, T.-Y. Fan, M.-S. Cheng, S.-F. Liang, T.-C. Chien, S.-Y. Wu, Y.-L. Wang, F.-Z. Shaw, Y.-H. Huang, C.-H. Yang, J.-C. Chiou, C.-W. Chang, L.-C. Chou, C.-Y. Wu, "A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic SoC for Real-Time Epileptic Seizure Control," in Int. Solid State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 286-287, Feb. 2013.

2012

  • Y.-H. Shih, T.-J. Chen, C.-H. Yang, and H. Chiueh, “Hardware-Efficient EVD Processor Architecture in FastICA for Epileptic Seizure Detection,” in Proc. Asia Pacific Signal and Information Processing Association (APSIPA), Special Session, Dec. 2012.
  • T.-J. Chen, C. Jeng, S.-T. Chang, H. Chiueh, and C.-H. Yang, “Hardware Implementation of a Real-Time Epileptic Seizure Detector,” in VLSI Design/CAD Symposium (VLSI-CAD), Aug. 2012.
  • T.-J. Chen, Y.-H. Shih, C.-H. Yang, H. Chiueh, and S. F. Liang, “A Low-Power Signal Processor with p. 3/4an ICA Engine for Real-Time Epileptic Seizure Detection,” in Neural Interface Conference (NIC), Jun. 2012.

2011

  • T.-H. Yu, C.-H. Yang, and D. Marković, “An Energy-Efficient VLSI Architecture for Wideband Spectrum Sensing for Cognitive Radios,” in Proc. Global Communications Conference (GLOBECOM), Dec. 2011, pp. 1-6.
  • F.-L. Yuan, C.-H. Yang, and D. Marković, “A Hardware-Efficient VLSI Architecture for Hybrid Sphere-MCMC Detection,” in Proc. Global Communications Conference (GLOBECOM), Dec. 2011, pp. 1-6.
  • V. Karkare, S. Gibson, C.-H. Yang, H. Chen, and D. Marković, “A 75μW, 16-Channel Neural Spike-Sorting Processor with Unsupervised Clustering,” in Proc. Int. Symposium on VLSI Circuits (VLSI Circuits), June 2011, pp. 252-253.
  • T.-H. Yu, C.-H. Yang, D. Čabrić, and D. Marković, “A 7.4mW 200MS/s Spectrum Sensing Digital Baseband Processor for Cognitive Radios,” in Proc. Int. Symposium on VLSI Circuits (VLSI Circuits), June 2011, pp. 254-255.

2005 - 2010

  • C.-H. Yang, T.-H. Yu, and D. Marković, “A 5.8mW 3GPP-LTE Compliant 8x8 MIMO Sphere Decoder Chip with Soft-Outputs,” in Proc. Int. Symposium on VLSI Circuits (VLSI Circuits), June 2010, pp. 209-210.
  • C.-H. Yang and D. Marković, “A 2.89mW 50GOPS 16x16 16-Core MIMO Sphere Decoder in 90nm CMOS,” in Proc. European Solid-State Circuits Conference (ESSCIRC), Sep. 2009, pp. 344-348.
  • C.-H. Yang and D. Marković, “A Multi-Core Sphere Decoder VLSI Architecture for MIMO Communications,” in Proc. Global Communications Conference (GLOBECOM), Dec. 2008, pp. 3297-3301.
  • R. Nanda, C.-H. Yang, D. Marković, “DSP Architecture Optimization in Matlab/Simulink Environment,” in Proc. Int. Symposium on VLSI Circuits (VLSI Circuits), June 2008, pp. 192-193.
  • C.-H. Yang and D. Marković, “A Flexible VLSI Architecture for Extracting Diversity and Spatial Multiplexing Gains in MIMO Channels,” in Proc. Int. Conference on Communications (ICC), May 2008, pp. 725-731.
  • C.-H. Yang, K.-H. Chen, T.-D. Chiueh, “A 1.2V 6.7mW Impulse-Radio UWB Baseband Transceiver,” in Int. Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, Feb. 2005, pp. 442-443.

Book Chapters

  • D. Marković and R. W. Brodersen, DSP Architecture Design Essentials, (Chapter 14, Chapter 15: MHz-rate Decoders, Co-author), Springer 2011.

Forums

  • Z.-S. Fu, Y.-C., Lee, and C.-H. Yang, Presentation at the ISSCC Student Research Preview, Feb. 2022.
  • S.-A. Huang and C.-H. Yang, Presentation at the ISSCC Student Research Preview, Feb. 2018.
  • W.-C. Liu, C.-D. Chan, C.-W. Lo, S.-J. Jou, and C.-H. Yang, Presentation at the ISSCC Student Research Preview, Feb. 2014.

Patents

US

  • C.-H. Yang, S.-H. Chen, C.-W. Liu, "Algorithm system of deep reinforcement learning and algorithm method thereof," US 2025/0165793 A1, May 2025.
  • C.-F. Tsai, C.-H. Yang, C.-Y. Du, "Machine learning optimization circuit and method thereof," US 2024/0281209 A1, Aug. 2024.
  • C.-H. Yang, L.-H. Lin, Y.-L. Kang, Y.-H. Lin, C.-M. Lai, "Modulo divider and modulo division operation method for binary data," US 2024/0220210 A1, Jul. 2024.
  • C.-H. Yang, C.-C. Kao, C.-H. Chen, "Electronic device and method for accelerating canonical polyadic decomposition," US 2024/0012873 A1, Jan. 2024.
  • J.-H. Hung, C.-H. Yang, "Portable Genome Sequencing and Genotyping Device and Operating Method Thereof," US 11,840,729, Dec. 2023.
  • C.-H. Yang, L.-H. Lin, Y.-L. Kang, L.-C. Su, "Modular multiplication circuit and corresponding modular multiplication method," US 11,829,731, Nov. 2023.
  • Z.-S. Fu, W.-C. Huang, C.-H. Yang, Z. Zhang, T. Wesley, J. Botimer, "Processing unit architectures and techniques for reusable instructions and data," US 2023/0072556 A1, Sep. 2023.
  • J.-H. Hung, C.-H. Yang, Y.-C. Wu, Y.-L. Chen, C.-H. Yang, "Data Processing System for Processing Gene Sequencing Data," US 2023/0154570 A1, May 2023.
  • C.-H. Yang, Y.-P. Wang, C.-C. Wen, D.-Z. Liu, C.-J. Huang, "Iterative detection and decoding circuit, iterative detection and decoding method and MIMO receiver," US 11,431,440, Aug. 2022.
  • J.-H. Hung, C.-H. Yang, Y.-C. Wu, "Method and system for DNA sequence alignment," US 11,302,419 B2, Apr. 2022.
  • C.-H. Yang, P.-H. Hsieh, H.-T. Lin, "Wireless power transfer system supplying power required by adiabatic circuit," US 10,367,376, July, 2019.
  • S.-J. Jou, C.-H. Yang, W.-C. Liu, C.-W. Lo, C.-D. Chan, "Master-slave flipflop," US 9,991,876, June 2018.
  • Y.-L. Ueng, W.-C. Sun, W.-H. Wu, C.-H. Yang, “SISO (Soft Input Soft Output) System for Use in a Wireless Communication System and Operational Method Thereof,” US 9,973,217, May 2018.
  • M.-R. Li, C.-H. Yang, and Y.-L. Ueng, “Extreme index finder and finding method thereof,” US 9,748,968, Aug. 2017.
  • C.-H. Yang, H.-M. Liu, Y.-J. Lin, “Data allocating apparatus, signal processing apparatus, and data allocating method,” US 9,529,539, Dec. 2016.
  • C.-H. Yang, P.-H. Hsieh, C.-Y. Lee, “Energy Recycling Systems and Recycling Method Thereof,” US 9,431,910, Aug. 2016.
  • C.-H. Yang and Y.-C. Tsai, “Multiple Input Multiple Output Wireless Communication System and Channel Decomposition Method Thereof,” US 9,306,641, Apr. 2016.
  • S.-J. Jou, C.-H. Yang, W.-C. Liu, C.-W. Lo, C.-D. Chan, “Sampling Circuit and Master-Slave Flip-Flop,” US 9,608,603 B2, Mar. 2016.
  • C.-H. Yang, C.-E. Chen, and C.-W. Jou, “Method and system for constrained power allocation in the multi-input multi-output systems,” US 9,231,674, Jan. 2016.
  • C.-H. Yang and Y.-C. Tsai, “Multiple Input Multiple Output Wireless Communication System and Channel Decomposition Method Thereof,” US 9,231,679, Jan. 2016.
  • Y.-L. Ueng, C.-H. Yang, M.-R. Li, “Unequal Bit-reliability Information Storage Method for Communication and Storage Systems,” US 9,058,880, Jun. 2015.

Taiwan

  • 楊家驤, 陳世豪, 劉志尉, "深度強化學習的演算系統及其演算方法," TW I854896, Sep. 2024.
  • 蔡介夫, 楊家驤, 杜承諺, "機器學習優化電路及其方法," TW I835562, Mar. 2024.
  • 楊家驤, 林亮昕, 康譽齡, 林育輝, 賴志明, "用於二進制資料的模數除法器和模除運算方法," TW I823737, Nov. 2023.
  • 楊家驤, 林亮昕, 康譽齡, 蘇莉祺, "模數乘法電路與對應之計算模數乘法之方法," TW I802095, May 2023.
  • 楊家驤, 高禎謙, 陳昭宏, "加速典範多元分解的電子裝置和方法," TW I801316, May 2023.
  • 洪瑞鴻, 楊家驤, 吳易忠, 陳彥龍, 楊仲萱, "用於處理基因定序資料的資料處理系統," TW I785847, Dec. 2022.
  • 洪瑞鴻, 楊家驤, "可攜式基因定序與定型裝置及其操作方法," TW I780455, Oct. 2022.
  • 楊家驤, 王耀斌, 文及志, 柳德政, 黃崇榮, "迭代式檢測與解碼電路、迭代式檢測與解碼方法及多輸入多輸出接收機," TW I739074, Sep. 2021.
  • 洪瑞鴻, 楊家驤, 吳易忠, "用於基因定序資料的資料處理方法與系統," TW I636372, Sep. 2018.
  • 李茂睿, 楊家驤, 翁詠祿, "數值尋找器以及數值尋找方法," TW I600284, Sep. 2017.
  • 楊家驤, 謝秉璇, 林欣慈, "供應絕熱電路操作之無線電力傳輸系統,＂TW I568124, Jan. 2017.
  • 楊家驤, 劉浩皿, 林詠仁, "資料分配裝置、訊號處理裝置及其資料分配方法," TW I564735, Jan. 2017.
  • 翁詠祿, 孫唯晟, 吳維軒, 楊家驤, "疊代式解碼裝置、疊代式訊號檢驗裝置與資訊更新方法," TW I555339, Oct. 2016.
  • 翁詠祿, 楊家驤, 李茂睿, "用於通訊或儲存系統之非均等位元可靠度軟式資訊儲存方法," TW I550633, Sep. 2016.
  • 楊家驤, 蔡雨澄, "多輸入多輸出無線通信系統及其通道分解方法," TW I543556, July 2016.
  • 楊家驤, 蔡雨澄, "多輸入多輸出無線通信系統及其通道分解方法,” TW I543555, July 2016.
  • 楊家驤, 陳喬恩, 周俊瑋, "在多重輸入多重輸出無線通訊系統中限制功率分配的方法及裝置," TW I542167, July 2016.
  • 楊家驤, 謝秉璇, 李承晏, "能量回收系統及其回收方法," TW I539749, June 2016.
  • 周世傑, 楊家驤, 劉瑋昌, 羅其偉, 詹慶達, "取樣電路及主從正反器," TW I517584, Jan. 2016.