Computer-Aided VLSI System Design


Fall 2011

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  • [2011/12/22] The project presentation schedule is posted.


  • [2011/12/08] Since the .13 process can be applied for the whole design flow, there is no need to switch back to the .18 process.


  • [2011/11/15] For HW3 submission, please 1) clearly state the value of parameter "CYCLE" (the cycle time that passes gate-level simulation) in your report, and 2) include file LMFE.sdf in your submission.


  • [2011/11/04] Please check the announcement for midterm exam on 11/11.


  • [2011/11/04] Please check your HW1 and HW2 grades and let TA Chia-Wei Chen know if there is any problem.


  • [2011/11/04] Lab 231 servers are unstable recently because of some students' unsuitable disc space management.
    Please be aware of the following suggestions:

    #1: Check your used disc space by
    using command "ls" or "ll" to show the information of files.
    (The unit is in bytes.)
    or using command "du -m -s /home/raid2_2/user98/rXXXXXX/ " (change to your own path)
    (The unit is in megabytes.)

    #2: If your used space is over 2GB, there must be something wrong (unless you know what you do).
    Kill unnecessary files, especially .vcd waveform files.

    #3: Since the .vcd waveform files occupy the most space, you may modify the testbenchs in HW3 and HW4 as follows:
    //==============Original==============
    $dumpfile("LMFE1.vcd");
    $dumpvars;
    //$fsdbDumpfile("LMFE1.fsdb");
    //$fsdbDumpvars;

    //==============Modified==============
    //$dumpfile("LMFE1.vcd");
    //$dumpvars;
    $fsdbDumpfile("LMFE1.fsdb");
    $fsdbDumpvars;

    #4: However even with the .fsdb file, the waveform file can grow with respect to the number of simulation cycles.
    Please use "Ctrl+C" to quit simulation if the simulator stucks. The waveform of incomplete simulation can still be used for debugging.
    Moreover, you can hide waveform generation to shorten your simulation time.
     

  • [2011/10/13] For HW2 submission, please name your design as StudentID_HW2_CTE_vk.v, where k = 1, 2, ... denoting version k.


  • [2011/10/08] Correction to HW2-Verilog_2011.pdf was made (negative signs for RGB to YUV conversion in page 11).


  • [2011/10/07] 在執行ncsim的時候, 我們要看simulation的波形結果的話需要吐出.fsdb或者.vcd檔, 這兩個檔案都很大, 尤其是.vcd檔案.
    模擬中若.fsdb檔沒有寫完成, ncsim就不會結束, 除非使用者強制中止(ctrl+c), 否則吐出來的波形檔就會越來越大.

    以下有兩個建議:
    1. ncsim吐波形出來會用掉不少硬碟空間, 所以跑ncsim一段時間後, 若一直沒有結束, 要按ctrl+c強制中止, 才不會導致波形一直寫入硬碟空間.
    2. 本來的testbench是要收到design吐出的訊號才會執行中止, 建議testbench要再加上一個條件, 就是跑超過幾個cycle就會中止(這個範圍可以大一點, 避免未做完模擬就停掉).
     

  • [2011/09/23] Lecture materials (syllabus.pdf and LN0-announce.pdf) of 9/16 updated


  • [2011/09/23] Link to Course Forum (Ceiba 討論看板) added in Links page


  • [2011/09/20] Please submit your homework assignments online using ftp through

    host IP:      140.112.175.123

    port:           9527

    username:  cvsd_students

    password:  cvsd2011


  • [2011/09/15] Please check back frequently to this page for announcements.