Electronic Circuits Lab-Faculty

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Address: Graduate Institute of Electronics Engineering, NTU б@
No.1, Sec.4, Roosevelt Rd. б@
Taipei, Taiwan, 10617, R.O.C.
Office: 240
Tel: (886-2)3366-3629
Fax: (886-2)2367-1909
E-Mail: lsi@ntu.edu.tw

Shen-Iuan Liu (Sбж88бVMбж93бVSMбж03-Fбж10) was born in Keelung, Taiwan, Republic of China, 1965. He received the B.S. and Ph.D. degrees in electrical engineering from National Taiwan University (NTU), Taipei, Taiwan, R.O.C., in 1987 and 1991, respectively. During 1991бV1993, he served as a second lieutenant in the Chinese Air Force. During 1991бV1994, he was an Associate Professor in the Department of Electronic Engineering, National Taiwan Institute of Technology. He joined the Department of Electrical Engineering, NTU, in 1994, where he has been a professor since 1998. Now, he is a distinguished professor in NTU since Aug. 2010. He was the Director of Graduate Institute of Electronics Engineering in NTU, 2013-2016. His research interests are in analog and digital integrated circuits and systems.
In 2004-2008, Dr. Liu has served as chair of the IEEE SSCS Taipei Chapter, which achieved the Best Chapter Award in 2009. He has served as general chair of the 15th VLSI Design/CAD Symposium, Taiwan, R.O.C. (2004) and as Program Co-chair of the Fourth IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, Fukuoka, Japan (2004). He was the recipient of the Engineering Paper Award from the Chinese Institute of Engineers in 2003, the Young Professor Teaching Award from MXIC Inc., the Research Achievement Award from NTU, the Outstanding Research Award from National Science Council in 2004, and the Outstanding Research Award from Ministry of Science and Technology in 2014. He achieved Teaching Excellence Award from NTU in 2022. He was awarded the Himax Chair Professorship at NTU in 2010. He has served as a technical program committee member for ISSCC in 2006-2008, IEEE VLSI-DAT in 2008-2012, and A-SSCC in 2005-2012. He also served as the technical program committee co-chair and chair for A-SSCC 2010 and 2011, respectively. He was an Associate Editor for IEEE JOURNAL OF SOLID-STATE CIRCUITS in 2006-2009 and a Guest Editor for IEEE JOURNAL OF SOLID-STATE CIRCUITS Special Issue in Dec. 2008 and Nov. 2012. He was an Associate Editor for IEEE TRANS. ON CIRCUITS AND SYSTEMSбXII: EXPRESS BRIEFS in 2006-2007. He was an Associate Editor for IEEE TRANS. ON CIRCUITS AND SYSTEMSбXI: REGULAR PAPERS in 2008-2009. He was the Editorial Board of Research Letters in Electronics in 2008-2009. He was an Associate Editor for IEICE (The Institute of Electronics, Information and Communication Engineers) TRANS. ON ELECTRONCIS in 2008-2011. He is an Associate Editor for ETRI Journal, and also an Associate Editor for Journal of Semiconductor Technology and Science, Korea, from 2009. He was a recipient of the Best Paper Awards in the 2020 and 2021 International Symposium on VLSI Design, Automation and Test, and in the 2023 International VLSI Symposium on Technology, Systems and Applications. He is a Fellow of IEEE.

Publication Lists:
(A). Journals
(B). Local and international Conferences
(C). Articles
(D). Patents

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(A). Journals

270. Yuan-Pang Huang and Shen-Iuan Liu, бз A 48-Gb/s baud-rate PAM-4 receiver using modified time-interpolated latchesби, accepted by IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 69, no. , pp., 2024.

269. Hsi-Kai Peng and Shen-Iuan Liu, бзA 12.93-16Gb/s reference-less baud-rate CDR circuit with one-tap DFE and semirotational frequency detectionби, IEEE Trans. Very Large Scale Integration Systems, vol. 32, no. 4, pp. 787-791, April 2024.

268. Yi-Hao Lan and Shen-Iuan Liu, бзA 0.079-pJ/b/dB 32-Gb/s 2x half-baud-rate CDR circuit with frequency detectorби, IEEE Trans. Very Large Scale Integration Systems, vol. 32, no. 4, pp. 704-713, April 2024.

267. Po-Yuan Chou, Wei-Ming Chen and Shen-Iuan Liu, бзA 16-Gb/s baud-rate CDR circuit with one-tap speculative DFE and wide frequency capture rangeби, IEEE Trans. Very Large Scale Integration Systems, vol. 32, no. 3, pp. 480-484, March 2024.

266. Zhi-Heng Kang and Shen-Iuan Liu, бзA 1.6GHz DPLL using feedforward phase-error cancellationби, IEEE Journal of Solid-State Circuits, vol. 58, no. 3, pp. 806-816, March 2023.

265.Wen-Chi Huang and Shen-Iuan Liu, бзA 1.45-pJ/b 16-Gb/s edge-based sub-baud-rate digital CDR circuitби, IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 69, no. 12, pp. 4709-4713, Dec. 2022.

264.Yao-Hung Tsai and Shen-Iuan Liu, "A 0.0067-mm2 12-bit 20-MS/s SAR ADC using digital place-and-route tools in 40-nm CMOSби, IEEE Trans. Very Large Scale Integration Systems, vol. 30, no. 7 , pp. 905-914, July 2022.

263.Jia-Rong Chang and Shen-Iuan Liu, "A 2-3 GHz fast-locking PLL using phase error compensatorби, IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 69, pp. 2026-2030, April 2022.

262.Wei-Ming Chen, Yun-Sheng Yao and Shen-Iuan Liu, "A 20-Gb/s jitter-tolerance-enhanced digital CDR with one-tap DFEби, IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 69, pp. 894-898, March 2022.

261.Yuan Cheng Qian, Yen-Yu Chao and Shen-Iuan Liu, "A low-jitter sub-sampling PLL with a sub-sampling DLLби, IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 69, pp. 269-273, Feb. 2022.

260.Yun-Sheng Yao, Chang-Cheng Huang and Shen-Iuan Liu, "A wide-range FD for referenceless baud-rate CDR circuitsби, IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 69, pp. 60-64, Jan. 2022.

259.Wei-Ming Chen, Yun-Sheng Yao and Shen-Iuan Liu, "A 10.4-16-Gb/s reference-less baud-rate digital CDR with one-tap DFE using a wide-range FDби, IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 68, pp. 4566-4575, Nov. 2021.

258.Yun-Sheng Yao, Chang-Cheng Huang and Shen-Iuan Liu, ""A jitter-tolerance-enhanced digital CDR circuit using background loop gain controllerби, IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 68, pp. 1837-1840, June 2021.

257.Hsin-Tung Jen, Gayathri Pillai,Shen-Iuan Liu and Sheng-Shian Li, "High-Q support transducer MEMS resonators enabled low phase noise oscillatorsби,IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, vol. 68, no. 4, pp. 1387-1398, April 2021.

256.Ming-Han Chou and Shen-Iuan Liu, " A Type-I PLL with foreground loop bandwidth calibrationби, IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 68, pp. 1103-1107, April 2021.

255.Yong-Ru Lu and Shen-Iuan Liu,Yu-Che Yang, Han-Chang Kang, Chih-Lung Chen, Ka-Un Chan, and Ying-Hsi Lin,бз A 2.4-3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 68, pp. 873-877, March 2021.

254.Shun-Chi Chang and Shen-Iuan Liu,бз A 5-Gb/s adaptive digital CDR circuit with SSC capability and enhanced high-frequency jitter tolerance", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 68, pp. 161-164, Jan. 2021.

253.Ming-Chia Chang and Shen-Iuan Liu," An indoor photovoltaic energy harvester using time-based MPPT and on-chip photovoltaic cell", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 67, pp. 2432-2436, Nov. 2020.

252.Ming-Han Chou and Shen-Iuan Liu," A 2.4 GHz area-efficient and fast-locking subharmonically injection-locked type-I PLLби, IEEE Transactions on Very Large Scale Integration Systems, vol. 28, no. 11, pp. 2474-2478, Nov. 2020.

251.Kuan-Lin Fu and Shen-Iuan Liu," A 64 Gbps PAM-4 optical receiver with amplitude/phase correction and threshold voltage/data level calibration", IEEE Transactions on Very Large Scale Integration Systems, vol. 28, no. 7, pp. 1726-1735, July 2020.

250.Guan-Yu Su and Shen-Iuan Liu," A 1.22 mW 2.4 GHz PLL using a single-ring-oscillator-based integrator with background frequency calibration", IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 67, no. 7, pp. 2169-2179, July 2020.

249.Chung-Jen Kuo and Shen-Iuan Liu, бзA 13.56MHz current-mode wireless power receiver with energy-investment capability", IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 205-209, Feb. 2020.

248.Yu-Kai Chiu and Shen-Iuan Liu, "A PVT-tolerant MDLL using a frequency calibrator and a voltage monitor", IEEE Transactions on Very Large Scale Integration Systems, vol. 27, no. 7, pp. 2698-2702, Nov. 2019.

247.Yi-An Chang and Shen-Iuan Liu, "A 13.4MHz relaxation oscillator with temperature compensation", IEEE Transactions on Very Large Scale Integration Systems, vol. 27, no. 7, pp. 1725-1729, July 2019.

246.Yi-An Chang, Trio Adiono, Amy Hamidah, and Shen-Iuan Liu, "An on-chip relaxation oscillator with comparator delay compensation", IEEE Transactions on Very Large Scale Integration Systems, vol. 27, no. 4, pp. 969-973, April 2019.

245.Cheng-En Hsieh and Shen-Iuan Liu, "A 2.4 GHz frequency-drift-compensated phase-locked loop with 2.43ppm/вXC temperature coefficient", IEEE Transactions on Very Large Scale Integration Systems, vol. 27, no. 3, pp. 501-510, March 2019.

244.Che-Wei Tien and Shen-Iuan Liu, "A PVT-tolerant injection-locked clock multiplier with a frequency calibrator using a delay time detector", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 66, no. 2, pp. 177-181, Feb. 2019.

243.Che-Wei Tien, and Shen-Iuan Liu, "A digital phase-locked loop with background supply voltage sensitivity minimization", IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 65, no. 6, pp. 1830-1839, June 2018.

242.Kuan-Yu Chen, Wei-Yung Chen, and Shen-Iuan Liu, "A 0.31pJ/bit 20Gb/s DFE with 1 discrete tap and 2 IIR filters feedback in 40nm-LP CMOS", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 64, no. 11, pp.1282-1286, Nov. 2017.

241.Ye-Sing Luo and Shen-Iuan Liu, "A voltage multiplier with adaptive threshold voltage compensation", IEEE Journal of Solid-State Circuits, vol. 52, No. 8, pp. 2208-2214, Aug. 2017.

240.Kuan-Yu Chen, Wei-Yung Chen, and Shen-Iuan Liu, "A 0.035pJ/bit/dB 20Gb/s adaptive linear equalizer with an adaptation time of 2.68us", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 64, pp. 645-649, June 2017.

239.Wun-Jian Su and Shen-Iuan Liu, "A 5Gb/s voltage-mode transmitter using adaptive time-based de-emphasis", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, pp. 959-968, April 2017.

238.Yen-Hsiang Tseng, Che-Wei Yeh, and Shen-Iuan Liu, "A 2.25-2.7 GHz area-efficient subharmonically injection-locked fractional-N frequency synthesizer with a fast-converging correlation loop", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, pp. 811-822, April 2017.

237.Chih-Lu Wei and Shen-Iuan Liu, "A digital PLL using oversampling delta-sigma TDC", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 63, pp. 633-637, July 2016.

236.Ting-Kuei Kuan and Shen-Iuan Liu, "A bang-bang phase-locked loop using automatic loop gain control and loop latency reduction techniques", IEEE Journal of Solid-State Circuits, vol. 51, pp. 821-831, April 2016.

235.Liang-Jen Chen and Shen-Iuan Liu, "A 12-bit 3.4MS/s two-step cyclic time-domain ADC in 0.18гgm CMOS", IEEE Transactions on Very Large Scale Integration Systems, vol. 24, pp. 1470-1483, April 2016.

234.Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, and Charlie Chung-Ping Chen, "A 6.7 MHz to 1.24 GHz 0.0318 mm2 fast-locking all-digital DLL using phase-tracing delay unit in 90 nm CMOS", IEEE Journal of Solid-State Circuits, vol. 51, pp.412-427, Feb. 2016.

233.Liang-Jen Chen and Shen-Iuan Liu, "A 10-bit 40MS/s time-domain two-step ADC with short calibration time", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 63, pp. 126-130, Feb. 2016.

232.Kai-Hui Zeng, Ting-Kuei Kuan and Shen-Iuan Liu, "A sub-harmonically injection-locked all-digital PLL without main divider", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 62, pp. 1033-1037, Nov. 2015.

231.Ting-Kuei Kuan and Shen-Iuan Liu, "A loop gain optimization technique for integer-N TDC-based phase-locked loops", IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 62, pp. 1873-1882, July 2015.

230.Chih-Lu Wei, Ting-Kuei Kuan and Shen-Iuan Liu, "A sub-harmonically injection-locked PLL with calibrated injection pulse width", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 62, pp. 548-552, June 2015.

229.Yu-Hsun Chien, Kuan-Lin Fu and Shen-Iuan Liu, "A 3-25 Gb/s 4-channel receiver with noise-canceling TIA and power scalable LA", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 61, pp. 845-849, Nov. 2014.

228.Yu-Hsuan Chiang and Shen-Iuan Liu, "Nanopower CMOS relaxation oscillators with sub-100ppm/oC temperature coefficient", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 61, pp. 661-665, Sept. 2014.

227.I-Ting Lee, Shih-Han Ku and Shen-Iuan Liu, "An all-digital de-spreading clock generator", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 61, pp. 16-20, Jan. 2014.

226.Yu-Hsuan Chiang and Shen-Iuan Liu, "A submicrowatt 1.1MHz CMOS relaxation oscillator with temperature compensation", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 60, pp. 837-841, Dec. 2013.

225.Ye-Sing Luo, Jiun-Ru Wang, Wei-Jen Huang, Je-Yu Tsai, Yi-Fang Liao, Wan-Ting Tseng, Chen-Tung Yen, Pai-Chi Li and Shen-Iuan Liu, "Ultrasonic Power/Data Telemetry and Neural Stimulator with OOK-PM Signaling", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 60, pp. 827-831, Dec. 2013.

224.Pin-Hao Feng and Shen-Iuan Liu, "A 300GHz divide-by-2 CMOS ILFD using frequency boosting technique", IEEE Microwave and Wireless Components Letters, vol. 23, pp. 599-601, Nov. 2013.

223.Shih-Yuan Kao and Shen-Iuan Liu, "A 10-Gb/s adaptive parallel receiver with joint XTC and DFE using power detection", IEEE Journal of Solid-State Circuits, vol. 48, pp. 2815-2826, Nov. 2013.

222.I-Ting Lee, Shih-Han Ku, and Shen-Iuan Liu, "An all-digital spread-spectrum clock generator with self-calibrated bandwidth", IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 60, pp. 2813-2822, Nov. 2013.

221.Yan-Yu Lin and Shen-Iuan Liu, "4-Gb/s parallel receivers with adaptive FEXT cancellation by pulse-width and amplitude calibrations", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 60, pp. 622-626, Oct. 2013.

220.I-Ting Lee, Kai-Hui Zeng, and Shen-Iuan Liu, "A 4.8GHz divider-less sub-harmonically injection-locked all-digital PLL with FOM of -252.5dB", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 60, pp. 547-551, Sept. 2013.

219.Yan-Yu Lin and Shen-Iuan Liu, "4-Gb/s parallel receivers with adaptive far-end crosstalk cancellation", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 60, pp. 252-256, May 2013.

218.Pin-Hao Feng and Shen-Iuan Liu, "A current-reused injection-locked frequency multiplication/division circuit in 40-nm CMOS", IEEE Transactions on Microwave Theory and Techniques, Vol. 61, pp. 1523-1532, April 2013.

217.I-Ting Lee, Yun-Ta Tsai, and Shen-Iuan Liu, "A wide-range PLL using self-healing prescaler/VCO in 65-nm CMOS", IEEE Trans. on VLSI Systems, vol. 21, pp. 250-258, Feb. 2013.

216.Yi-Chieh Huang and Shen-Iuan Liu, "A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing", IEEE Journal of Solid-State Circuits, vol. 48, pp.417-428, Feb. 2013.

215.Pin-Hao Feng and Shen-Iuan Liu, "Divide-by-three injection-locked frequency dividers over 200GHz in 40-nm CMOS", IEEE Journal of Solid-State Circuits, vol. 48, pp. 405-416, Feb. 2013.

214.Shih-Yuan Kao and Shen-Iuan Liu, "A 7.5-Gb/s one-tap FFE transmitter with adaptive far-end crosstalk cancellation using duty cycle detection", IEEE Journal of Solid-State Circuits, vol. 48, pp. 391-404, Feb. 2013.

213.I-Ting Lee, Yun-Ta Tsai, and Shen-Iuan Liu, "A leakage-current-recycling phase-locked loop in 65nm CMOS technology", IEEE Journal of Solid-State Circuits, vol. 47, pp. 2693-2700, Nov. 2012.

212.I-Ting Lee, Chiao-Hsing Wang, Ju-Rong Sha, Ying-Zong Juang, and Shen-Iuan Liu, "A D-band divide-by-3 injection-locked frequency divider in 65nm CMOS", IET Electronics Letters, vol. 48, pp. 1041-1042, Sept. 2012.

211.I-Ting Lee, Hung-Yu Lu, and Shen-Iuan Liu, "A 6GHz all-digital fractional-N frequency synthesizer using FIR-embedded noise filtering technique", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 59, pp. 267-271, May 2012.

210.Yi-Chieh Huang, Ping-Ying Wang, and Shen-Iuan Liu, "An all-digital jitter-tolerance measurement technique for CDR circuits", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 59, pp. 148-152, March 2012.

209.I-Ting Lee, Chiao-Hsing Wang, Chun-Lin Ko, Ying-Zong Juang, and Shen-Iuan Liu, "A 3.6mW 125.7~131.86GHz divide-by-4 injection-locked frequency divider in 90nm CMOS", IEEE Microwave and Wireless Components Letters, vol. 22, pp. 132-134, March 2012.

208.I-Ting Lee, and Shen-Iuan Liu, "G-Band injection-locked frequency dividers using гk-type LC Networks", IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 59, pp. 315-323, Feb. 2012.

207.Ke-Hou Chen, and Shen-Iuan Liu, "Inductorless wideband CMOS low-noise amplifiers using noise-canceling technique", IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 59, pp. 305-314, Feb. 2012.

206.Kun-Hung Tsai, and Shen-Iuan Liu, "A 104GHz phase-locked loop using a VCO at second pole frequency", IEEE Trans. on VLSI Systems, vol. 20, pp. 80-88, Jan. 2012.

205.Chang-Lin Hsieh, and Shen-Iuan Liu, "Decision feedback equalizers using back-gate feedback technique", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 58, pp. 897-901, Dec. 2011

204.Bo-Yu Lin, and Shen-Iuan Liu, "A 132.6GHz phase-locked loop in 65nm digital CMOS", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 58, pp. 617-621, Oct. 2011.

203.I-Ting Lee,Chiao-Hsing Wang, and Shen-Iuan Liu, "A current-reused divide-by-3 injection-locked frequency divider in 65nm CMOS", IET Electronics Letters, vol. 47, pp. 1029-1030, Sept. 2011.

202. Chang-Lin Hsieh, and Shen-Iuan Liu, "A 1~16Gb/s wide-range clock/data recovery circuit with bidirectional frequency detector", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 58, pp. 487-491, Aug. 2011.

201. Wei-Jen Huang, Shigeisa Nagayasu, and Shen-Iuan Liu, "A rail-to-rail class-B buffer with DC level-shifting current mirror and distributed Miller compensation for LCD column drivers", IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 58, pp. 1761-1772, Aug. 2011.

200. Bo-Yu Lin, and Shen-Iuan Liu, "A 113.92~118.08GHz injection-locked frequency divider with triple-split-inductor technique", IEEE Microwave and Wireless Components Letters, vol. 21, pp. 436-438, Aug. 2011.

199. Chao-Ching Hung, and Shen-Iuan Liu, "A 40GHz fast-locked all-digital phase-locked loop using modified bang-bang algorithm", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 58, pp.321-325, June 2011.

198. Bo-Yu Lin, and Shen-Iuan Liu, "Analysis and design of D-band injection-locked frequency dividers", IEEE Journal of Solid-State Circuits, vol. 46, pp.1250-1264, June 2011.

197. Shih-Yuan Kao and Shen-Iuan Liu, "A digitally-calibrated phase-locked loop with supply sensitivity suppression", IEEE Trans. on VLSI Systems, vol. 19, pp.592-602, April 2011.

196. Chao-Ching Hung, and Shen-Iuan Liu, "A noise-filtering technique for fractional-N frequency synthesizers", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 58, pp. 139-143, March 2011.

195. Wei-Jen Huang and Shen-Iuan Liu, "A PSRR-enhanced low-dropout regulator", IET Electronics Letters, vol. 47, pp. 17-18, Jan. 2011.

194. I-Ting Lee, Chiao-Hsing Wang, Bo-Yu Lin, and Shen-Iuan Liu, "A 258.16~259.95 GHz injection-locked frequency divider", IET Electronics Letters, vol. 46, pp. 1438-1439, Oct. 2010.

193. Jung-Yu Chang and Shen-Iuan Liu, "A phase-locked loop with background leakage current compensation", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 57, pp. 666-670, Sept. 2010.

192. Shih-Yuan Kao and Shen-Iuan Liu, "A 20Gbps transmitter with adaptive pre-emphasis in 65nm CMOS technology", IEEE Trans. Circuits and Systems-II: Express Briefs, pp. 319-323, May 2010.

191. Shih-Yuan Kao and Shen-Iuan Liu, "A 1.62/2.7Gbps adaptive transmitter with 2-tap pre-emphasis using a propagation-time detector", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 57, pp. 178-182, March 2010.

190. Jian-Hao Lu and Shen-Iuan Liu, "A merged CMOS digital near-end crosstalk canceller and analog equalizer for multi-lane serial-link receivers", IEEE Journal of Solid-State Circuits, vol. 45, pp. 433-446, Feb. 2010.

189. Mu-Chen Huang and Shen-Iuan Liu, "A 10MS/s to 100kS/s power-scalable fully-differential CBSC 10-bit pipelined ADC with adaptive biasing", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 57, pp. 11-15, Jan. 2010.

188. Jung-Yu Chang, and Shen-Iuan Liu, "A 1.5GHz phase-locked loop with leakage current suppression in 65nm CMOS", IET Circuits, Devices & Systems, vol. 3, pp. 350-358, Dec. 2009.

187. Chi-Nan Chuang, and Shen-Iuan Liu, "A 20MHz~3GHz wide-range multi-phase delay-locked loop", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 56, pp. 850-854, Nov. 2009.

186. Sheng-You Lin, and Shen-Iuan Liu, "A 1.5GHz all-digital spread spectrum clock generator", IEEE Journal of Solid-State Circuits, vol. 44, pp. 3111-3119, Nov. 2009.

185. Jian-Hao Lu, and Shen-Iuan Liu, "A 50Gb/s 10mW analog equalizer using transformer feedback technique in 65nm CMOS technology", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 56, pp. 783-787, Oct. 2009.

184. I-Ting Lee, Kun-Hung Tsai, and Shen-Iuan Liu, "A 104~112.8GHz CMOS injection-locked frequency divider", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 56, pp. 555-559, July 2009.

183. I-Hsin Wang, Hwei-Yu Lee, and Shen-Iuan Liu, "An 8-bit 20MS/s ZCBC time-domain analog-to-digital data converter", IEEE Trans. Circuits and Systems-II: Express Briefs, , vol. 56, pp. 545-549, July 2009.

182. Chao-Ching Hung, and Shen-Iuan Liu, "A leakage-compensated PLL in 65nm CMOS technology", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 56, pp.525-529, July 2009.

181. Mu-Chen Huang, and Shen-Iuan Liu, "A fully-differential comparator-based switched-capacitor delta-sigma modulator", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 56, pp. 369-373, May 2009.

180. Lan-Chou Cho, Chihun Lee, Chao-Ching Hung, and Shen-Iuan Liu, "A 33.6-to-33.8Gb/s burst-mode CDR in 90nm CMOS technology", IEEE Journal of Solid-State Circuits, vol. 44, pp. 775-783, March 2009.

179. Jian-Hao Lu, Ke-Hou Chen, and Shen-Iuan Liu, "A 10Gb/s inductorless CMOS analog equalizer with interleaved active feedback topology", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 56, pp. 97-101, Feb. 2009.

178. Jung-Yu Chang, Che-Wei Fan, Che-Fu Liang, and Shen-Iuan Liu, "A single-PLL UWB frequency synthesizer using multiphase coupled ring oscillator and current-reused multiplier", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 56, pp. 107-111, Feb. 2009.

177. Wei-Ming Lin, Shen-Iuan Liu, Chun-Hung Kuo, Chun-Huai Li, Yao-Jen Hsieh, and Chun-Ting Liu, "A phase-locked loop with self-calibrated charge pumps in 3гgm LTPS-TFT Technology", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 56, pp. 142-146, Feb. 2009.

176. Shao-Hung Lin, and Shen-Iuan Liu, "Bang-bang phase/frequency detectors for unilateral continuous-rate CDR circuits", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 55, pp. 1214-1217, Dec. 2008.

175. Chi-Nan Chuang, and Shen-Iuan Liu, "A 3~8GHz delay-locked loop with cycle jitter calibration", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 55, pp. 1094-1098, Nov. 2008.

174. Chih-Fan Liao, and Shen-Iuan Liu, "A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery", IEEE Journal of Solid-State Circuits, vol. 43, pp. 2492-2502, Nov. 2008.

172. Chao-Chyun Chen, and Shen-Iuan Liu, "An infinite phase shift delay-locked loop with voltage-controlled sawtooth delay line", IEEE Journal of Solid-State Circuits, vol. 43, pp. 2413-2421, Nov. 2008.

173. Che-Fu Liang, Hong-Lin Chu, and Shen-Iuan Liu, "10Gbps inductorless CDRs with digital frequency calibration", IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 55, pp. 2514-2524, Oct. 2008.

171. Shao-Ku Kao, and Shen-Iuan Liu, "A delay-locked loop with statistical background calibration", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 55, pp.961-965, Oct. 2008.

170. Lan-Chou Cho, Kun-Hung Tsai, Chao-Ching Hung, and Shen-Iuan Liu, "81.5~85.9GHz injection-locked frequency divider in 65nm CMOS", IET Electronics Letters, vol. 43, pp. 966-968, July 2008.

169. Wei-Jen Huang and Shen-Iuan Liu, "Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array", IET Circuits, Devices & Systems, vol. 2, pp. 306-316, June 2008.

168. Chihun Lee, Lan-Chou Cho, Jia-Hao Wu and Shen-Iuan Liu, "A 50.8-53GHz clock generator using a harmonic-locked PD in 0.13um CMOS", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 55, pp. 404-408, May 2008.

167. Che-Fu Liang, Sy-Chyuan Hwu, and Shen-Iuan Liu, "A jitter-tolerance-enhanced CDR using a GDCO-based phase detector", IEEE Journal of Solid-State Circuits, vol. 43, pp. 1217-1226, May 2008.

166. Chih-Fan Liao and Shen-Iuan Liu, "40-Gb/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90nm CMOS", IEEE Journal of Solid-State Circuits, vol. 43, pp. 642-655, March 2008.

165. Che-Fu Liang, Hsin-Hua Chen, and Shen-Iuan Liu, "A digital calibration technique for charge pumps in phase-locked systems", IEEE Journal of Solid-State Circuits, vol. 43, pp. 390-398, Feb. 2008.

164. Chuan-Kang Liang, Rong-Jyi Yang, and Shen-Iuan Liu, "An all-digital fast-locking programmable DLL-based clock generator", IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 55, pp. 361-369, Feb. 2008.

163. I-Hsin Wang, and Shen-Iuan Liu, "A 0.18гgm CMOS 1.25Gbps automatic gain control amplifier", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 55, pp. 136-140, Feb. 2008.

162. Chao-Chyun Chen, Jung-Yu Chang, and Shen-Iuan Liu, "A DLL-based variable-phase clock buffer", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 54, pp. 1702-1706, Dec. 2007.

161.Ding-Shiuan Shen and Shen-Iuan Liu, "A low-jitter spread spectrum clock generator using FDMP", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 54, pp. 979-983, Nov. 2007.

160. Chi-Nan Chuang and Shen-Iuan Liu, "A 0.5~5GHz wide-range multi-phase DLL with a calibrated charge pump", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 54, pp. 939-943, Nov. 2007.

159. Rong-Jyi Yang and Shen-Iuan Liu, "A 2.5GHz all-digital delay-locked loop in 0.13гgm CMOS technology", IEEE Journal of Solid-State Circuits, SC-42, pp. 2338-2347, Nov. 2007.

158, Chein-Lung Chen , Ke-Hou Chen, and Shen-Iuan Liu, "Efficiency-enhanced CMOS rectifier for wireless telemetry", IEE Electronics Letters, vol. 43, pp. 976-978, Aug. 2007.

157. Che-Fu Liang, Hsin-Hua Chen, and Shen-Iuan Liu, "Spur-suppression techniques for frequency synthesizers", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 54, pp. 653-657, Aug. 2007.

156. Chein-Lung Chen , Wei-Jen Huang, and Shen-Iuan Liu, "A CMOS low dropout regulator with dynamic zero compensation", IEE Electronics Letters, vol. 43, pp. 751-752, July 2007.

155. Shao-Ku Kao, Bo-Jiun Chen, and Shen-Iuan Liu, "A 62.5-625MHz anti-reset all-digital delay-locked loop", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 54, pp. 566-570, July 2007.

154. Lan-Chou Cho, Chihun Lee, and Shen-Iuan Liu, "A 1.2V 37-38.5GHz 8-phase clock generator in 0.13um CMOS technology", IEEE Journal of Solid-State Circuits, SC-42, pp.1261-1270, June 2007.

153. Chao-Chyun Chen, Sheng-Chou Lee and Shen-Iuan Liu, "A capacitor multiplication technique using a second-generation current conveyor in the loop filter of the phase-locked loops", International Journal of Electrical Engineering, vol. 14, pp.239-245, June 2007.

152. Che-Fu Liang, Sy-Chyuan Hwu, and Shen-Iuan Liu, "A multi-band burst-mode clock and data recovery circuit", IEICE Trans. on Electronics, vol. E90-C, pp. 802-810, April 2007.

151. I-Hsin Wang and Shen-Iuan Liu, "A CMOS 5-bit 5GSample/sec analog-to-digital converter in 0.13um CMOS", Journal of Semiconductor Technology and Science, pp. 28-35, March 2007.

150. Ke-Hou Chen, Jian-Hao Lu, Bo-Jiun Chen, and Shen-Iuan Liu, "An ultra-wideband 0.4-10GHz LNA in 0.18um CMOS", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 54, pp. 217-221, March 2007.

149. Rong-Jyi Yang and Shen-Iuan Liu, "A 40~550MHz harmonic-free all-digital delay-locked loop using a variable SAR algorithm", IEEE Journal of Solid-State Circuits, SC-42, pp. 361-373, Feb. 2007.

148. Chih-Fan Liao and Shen-Iuan Liu, "A broadband noise-canceling CMOS LNA for 3.1-10.6-GHz UWB receivers", IEEE Journal of Solid-State Circuits, SC-42, pp. 329-339, Feb. 2007.

147. Sung-Rung Han, Chi-Nan Chuang, and Shen-Iuan Liu, "A time-constant calibrated phase-locked loop with a fast-locked time", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 54, pp. 34-37, Jan. 2007.

146. Shao-Ku Kao and Shen-Iuan Liu, "All-digital fast-locked synchronous duty cycle corrector", IEEE Trans. Circuits and Systems-II: Express Briefs, vol.53 , pp. 1363-1367, Dec. 2006.

145. Wei-Jen Huang and Shen-Iuan Liu, "A sub-1V capacitor-free low-dropout regulator", IEE Electronics Letters, vol. 43, pp. 1395-1397, Nov. 2006.

144. Che-Fu Liang, Shih-Tsai Liu and Shen-Iuan Liu, "A calibrated pulse generator for impulse-radio UWB applications", IEEE Journal of Solid-State Circuits, SC-41, pp. 2401-2407, Nov. 2006.

143. Chien-Hung Kuo, Shr-Lung Chen, and Shen-Iuan Liu, "A magnetic field to digital converter using PWM and TDC techniques", IEE Proceedings of Circuits, Devices and Systems, vol. 153, pp. 247- 252, June 2006.

142. Shao-Ku Kao, and Shen-Iuan Liu, "All-digital clock deskew buffer with variable duty cycles", IEICE Trans. on Electronics, vol.E89-C, pp. 753-760, June 2006.

141. Rong-Jyi Yang, Kuan-Hua Chao, Sy-Chyuan Hwu, Chuan-Kang Liang and Shen-Iuan Liu, "A 155.52Mbps ~ 3.125Gbps continuous-rate clock and data recovery circuit", IEEE Journal of Solid-State Circuits, SC-41, pp. 1380-1390, June 2006.

140. You-Jen Wang, Shao-Ku Kao and Shen-Iuan Liu , "All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles", IEEE Journal of Solid-State Circuits, SC-41, pp. 1262-1274, June 2006.

139. Hsiang-Hui Chang, Jung-Yu Chang, Chun-Yi Kuo and Shen-Iuan Liu, "A 0.7-2GHz self-calibrated multiphase delay-locked loop", IEEE Journal of Solid-State Circuits, SC-41, pp.1051-1061, May 2006.

138. Rong-Jyi Yang, Kuan-Hua Chao and Shen-Iuan Liu, "A 200Mbps~2Gbps continuous-rate clock and data recovery circuit", IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 53, pp. 842-847, April 2006.

137. I-Hsin Wang, Jia-Liang Lin and Shen-Iuan Liu, "A 5bit, 10Gsamples/sec track-and-hold circuit with input feedthrough cancellation", IEE Electronics Letters, vol. 42, pp. 457-458, April 2006.

136. Chi-Nan Chuang and Shen-Iuan Liu, "A 1V phase locked loop with leakage compensation in 0.13um CMOS technology", IEICE Trans. on Electronics, vol.E89-C, pp. 295-299, March 2006.

135. Chun-Yi Kuo, Jung-Yu Chang, and Shen-Iuan Liu, "A spur-reduction technique for a 5-GHz frequency synthesizer", IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 53, pp. 526-533, March 2006.

134. Wei-Jen Huang, Sao-Hung Lu and Shen-Iuan Liu, "CMOS low dropout linear regulator with single Miller capacitor", IEE Electronics Letters, vol. 42, pp. 216- 217, Feb. 2006.

133. Weihsing Liu, Shen-Iuan Liu and Shui-Ken Wei, "CMOS differential-mode exponential voltage-to-current converters", Journal of Analog Integrated Circuits and Signal Processings, vol. 45, pp. 163-168, Nov. 2005.

132. Chia-Hsin Wu, Chun-Yi Kuo, and Shen-Iuan Liu, "Selective metal parallel shunting inductor and its VCO application", IEEE Trans. Circuits and Systems-I: Regular Papers, vol. , pp. 1811-1818, Sept. 2005.

131. Rong-Jyi Yang and Shen-Iuan Liu, "A fully integrated 1.7~3.125Gbps clock and data recovery circuit using a gated frequency detector", IEICE Trans. on Electronics, vol.E88-C, pp. 1726-1730, Aug. 2005.

130. Rong-Jyi Yang and Shen-Iuan Liu, "A wide-range multiphase delay-locked loop using mixed-mode VCDLs", IEICE Trans. on Electronics, vol. E88-C, pp. 1248-1252, June 2005.

129. Sung-Rung Han and Shen-Iuan Liu, "A single-path pulsewidth control loop with a built-in delay-locked loop", IEEE Journal of Solid-State Circuits, SC-40, pp. 1130-1135, May 2005.

128. Weihsing Liu, Shen-Iuan Liu and Shui-Ken Wei, "CMOS current-mode divider and its applications", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 52, pp. 145-148, March 2005.

127. Hsiang-Hui Chang and Shen-Iuan Liu, "A wide-range and fast-locking all-digital cycle-controlled delay-locked loop", IEEE Journal of Solid-State Circuits, SC-40, pp. 661-670, March 2005.

126. Chia-Hsin Wu, Wei-Sheng Chen, Chih-Hun Lee, and Shen-Iuan Liu, "CMOS wide-band amplifiers using multiple inductive-series peaking technique", IEEE Journal of Solid-State Circuits, SC-40, pp. 548-552, Feb. 2005.

124. Ming-Huang Liu, Wei-Yang Ou, Tsung-Yi Su, Kuo-Chan Huang and Shen-Iuan Liu, "A 1.5V 12-bit 16MS/s pipelined CMOS ADC with 68dB dynamic range", Journal of Analog Integrated Circuits and Signal Processings,vol. 41, pp. 269-278, Dec. 2004.

123. Hsiang-Hui Chang, Rong-Jyi Yang, and Shen-Iuan Liu, "Low jitter and multi-rate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection", IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 51, pp. 2356- 2364 , Dec. 2004.

122. Chien-Hung Kuo and Shen-Iuan Liu, "A 1V 10.7MHz fourth-order bandpass DS modulators using two switched-opamps", IEEE Journal of Solid-State Circuits, SC-39, pp. 2041-2045, Nov. 2004.

121. Rong-Jyi Yang, Shang-Ping Chen, and Shen-Iuan Liu, "A 3.125Gbps Clock and Data Recovery Circuit for the Projectsbase-LX4 Ethernet", IEEE Journal of Solid-State Circuits, SC-39, pp. 1356-1560, Aug. 2004.

120. Weihsing Liu and Shen-Iuan Liu,"Low-voltage and low-power CMOS voltage-to-current converter", IEICE Trans. on Electronics, vol. E87-C, pp. 1029-1033, June 2004.

119. Ming-Huang Liu, Wei-Yang Ou, Tsung-Yi Su, Kuo-Chan Huang and Shen-Iuan Liu, "A low-voltage low-power 13-bit 16MSPS CMOS pipelined ADC", IEEE Journal of Solid-State Circuits, SC-39, pp. 834-836, May 2004.

118.Weihsing Liu, Shen-Iuan Liu and Shui-Ken We, "CMOS exponential-control variable-gain amplifiers", IEE Proceedings of Circuits, Devices and Systems, vol. 151, pp. 83-86, April 2004.

117. Weihsing Liu, Shen-Iuan Liu and Shui-Ken Wei, "Low voltage and low power CMOS exponential-control variable-gain amplifier", IEICE Trans. on Fundamentals of Electronics. Communications and Computer Sciences, vol. E87-A, pp. 952-954, April 2004.

116. Chih-Hao Sun and Shen-Iuan Liu, "A Mixed-mode Synchronous Mirror Delay Insensitive to Supply and Load Variations", Journal of Analog Integrated Circuits and Signal Processings, vol. 39, pp. 75-80, April 2004.

115. Chien-Hung Kuo, Shr-Lung Chen and Shen-Iuan Liu, "Magnetic-to-digital converters using single-amplifier-based second-order delta-sigma modulators", IEEE Sensors Journal, vol. 4, pp. 226- 231, April 2004.

114. Sung-Rung Han and Shen-Iuan Liu, "A 500MHz~1.25GHz fast-locking pulsewidth control loop with presettable duty cycle", IEEE Journal of Solid-State Circuits, SC-39, pp. 463-468, March 2004.

113. Weihsing Liu and Shen-Iuan Liu, "Low-voltage CMOS voltage-mode divider and its application", IEICE Trans. on Electronics, vol. E87-A, pp. 330-334, Feb. 2004.

112. Hsiang-Hui Chang, Chien-Hung Kuo, Ming-Huang Liu, and Shen-Iuan Liu, "A sub-1V fourth-order bandpass delta-sigma modulator", Journal of Analog Integrated Circuits and Signal Processings, vol. 37, pp. 179-189, Dec. 2003.

111. Chia-Hsin Wu, Chih-Chun Tang, Kun-Hsien Li and Shen-Iuan Liu, "CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90вX delay network", IEE Proceedings of Circuits, Devices and Systems, vol. 150, pp. 439-444, Oct. 2003.

110. Weihsing Liu and Shen-Iuan Liu, CMOS Tunable 1/x Circuit and its Applications, IEICE Trans. on Fundamentals, vol. E-86A, pp. 1896-1899, July 2003.

109. Hsiang-Hui Chang, Giang-Kaai Dehng and Shen-Iuan Liu, "An 800Mb/s tracking clock recovery receiver for the IEEE P1394a serial bus", Bulletin of the College of Engineering, National Taiwan University, no. 88, pp. 87-96, June 2003.

108. Chia-Hsin Wu, Chih-Chun Tang, and Shen-Iuan Liu, Analysis of on-chip spiral inductors using the distributed capacitance model, IEEE Journal of Solid-State Circuits, SC-38, pp. 1040-1044, June 2003.

107. Shr-Lung Chen, Chien-Hung Kuo and Shen-Iuan Liu, CMOS Magnetic Field to Frequency Converter, IEEE Sensors Journal, vol. 3, pp. 241-245, April 2003.

106. Hsiang-Hui Chang, I-Hui Hua and Shen-Iuan Liu, A Spread Spectrum Clock Generator with Triangular Modulation, IEEE Journal of Solid-State Circuits, SC-38, pp. 673-676, April 2003.

105. Hsiang-Hui Chang, Jyh-Woei Lin, and Shen-Iuan Liu, A fast locking and low jitter delay-locked loop using DHDL, IEEE Journal of Solid-State Circuits, SC-38, pp. 343-346, Feb. 2003.

104. Weihsing Liu and Shen-Iuan Liu, CMOS exponential function generator, Electronics Letters, vol. 39, pp. 1-2, Jan. 2003.

103. Chien-Hung Kuo, Tzu-Chien Hsueh, and Shen-Iuan Liu, Multi-bit delta-sigma modulator using a modified DWA algorithm, Journal of Analog Integrated Circuits and Signal Processings, pp. 289-300, Dec. 2002.

102. Chih-Chun Tang and Shen-Iuan Liu, A 1V 5.8GHz low noise amplifier in a 0.35um standard CMOS process, Journal of the Chineses Institute of Electrical Engineering, Series E, vol. 9, No. 4, pp. 395-400, Nov. 2002.

101. Yuh-Shyan Hwang, Pei-Tzu Hung, Wei Chen, Shen-Iuan Liu, Systematic generation of current-mode linear transformation filters based on multiple output CCIIs, Journal of Analog Integrated Circuits and Signal Processings, pp. 123-134, Aug. 2002.

100. Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang and Shen-Iuan Liu, A wide-range delay-locked loop with a fixed latency of one clock cycle, IEEE Journal of Solid-State Circuits, SC-37, pp. 1021-1027, Aug. 2002.

99. Chih-Chun Tang, Chia-Hsin Wu, and Shen-Iuan Liu, Miniature 3D inductors in standard CMOS process, IEEE Journal of Solid-State Circuits, vol. 37, pp. 471-480, April 2002.

98. Chih-Chun Tang, Kun-Hsien Li, and Shen-Iuan Liu, 2.4GHz offset-canceling down-conversion mixer, Electronics Letters, vol. 38, pp. 395-396 , April 2002.

97. Jiann-Jong Chen, Hen-Wai Tsao and Shen-Iuan Liu, Voltage-mode MOSFET-C filters using operational transresistance amplifiers (OTRAs) with reduced parasitic capacitance effect, IEE Proceedings-Circuits Devices and Systems, vol. 148, pp. 242-249, Oct. 2001.

96. Chien-Hung Kuo, Shr-Lung Chen, Lee-An Ho and Shen-Iuan Liu, CMOS oversampling DS magnetic to digital converters, IEEE Journal of Solid-State Circuits, Vol. 36, pp. 1582-1586, Oct. 2001.

95. Giang-Kaai Dehng, Jyh-Woei Lin and Shen-Iuan Liu, A fast-lock mixed-mode DLL Using a 2-b SAR Algorithm, IEEE Journal of Solid-State Circuits, Vol. 36, pp. 1464-1471, Oct. 2001.

94. June-Ming Hsu,Guang-Kaai Dehng, Ching-Yuan Yang, Chu-Yuan Yang and Shen-Iuan Liu, Low-Voltage CMOS Frequency Synthesizer for ERMES Pager Application IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 48, pp. 826-834, Sept. 2001. (NSC87-2622-E-002-016)

93. Wei-Hung Chen, Giang-Kaai Dehng, Jong-Woei Chen and Shen-Iuan Liu, A 400MHz serial link for AS-memeory systems using a PWM scheme, IEEE Journal of Solid-State Circuits, Vol. 36, pp. 1498-1505, Oct. 2001.

92. Chih-Chun Tang, Chia-Hsin Wu, Wu-Sheng Feng, and Shen-Iuan Liu, A 2.4GHz low voltage CMOS down-conversion double-balanced mixer, IEICE Trans. on Electronics, Vol. E84-C, pp. 1084-1091, Aug. 2001.

91. Cheng-Chieh Chang, Ming-Lang Lin and Shen-Iuan Liu, CMOS current-mode exponential-control variable-gain amplifier, Electronics Letters, vol. 37, pp. 868-869, July 2001.

90. Shen-Iuan Liu, Tzong-Bang Yu and Hen-Wai Tsao, Pipeline direct digital frequency synthesizer using decomposition method, IEE Proceedings-Circuits Devices and Systems, vol. 148, pp. 141-144, June 2001. (NSC86-2215-E-002-038)

89. Chih-Chun Tang and Shen-Iuan Liu, Low voltage CMOS low noise amplifier using the planar interleaved transformer, Electronics Letters, vol. 37, pp. 497-498, April 2001.

88. Jiin-Long Lee and Shen-Iuan Liu, Integrator and Differentiator with time Constant multiplication Using a Current Feedback Amplifier, Electronics Letters, vol. 37, pp. 331-333, March 2001.

87. Ching-Yuan Yang and Shen-Iuan Liu, A one-wire approach for skew compensating clock distribution based on bidirectional techniques, IEEE Journal of Solid-State Circuits, SC-36, pp. 266-272, Feb. 2001. (NSC88-2219-E-002-024)

86. Cheng-Chieh Chang, Yuh-Shyang Hwang and Shen-Iuan Liu, Low-voltage analog tripler circuit, Journal of Analog Integrated Circuits and Signal Processing, vol. 26, pp. 125-128, Feb. 2001. (NSC-89-2215-E002-024)

85. Ming-Huang Liu and Shen-Iuan Liu, An 8-bit 10MS/s folding and interpolating ADC using the continuous-time auto-zero technique, IEEE Journal of Solid-State Circuits, SC-36, pp. 122-128, Jan. 2001.

84. Cheng-Chieh Chang and Shen-Iuan Liu, Pseudo-exponential function using MOSFETs in saturation, IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 47, pp. 1318-1321, Nov. 2000. (NSC89-2215-E-002-024)

83. Ching-Yuan Yang and Shen-Iuan Liu, Fast-switching frequency synthesizer with a discriminator-aided phase detector, IEEE Journal of Solid-State Circuits, SC-35, pp. 1445-1452, Oct. 2000. (NSC88-2219-E-002-024)

82. PoKi Chen, Shen-Iuan Liu and Jingshown Wu, A CMOS pulse-shrinking delay element for time interval measurement, IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 47, pp. 954-958, Sept. 2000.

81. Cheng-Chieh Chang and Shen-Iuan Liu, Current-mode full-wave rectifier and vector summation circuit, Electronics Letters, pp. 1599-1600, Sept. 2000.

80. Cheng-Chieh Chang and Shen-Iuan Liu, Current-mode pseudo-exponential circuit with tunable input range, Electronics Letters, vol. 36, pp. 1335-1336, Aug. 2000. (NSC89-2215-E-002-024)

79. Guang-Kaai Dehng, Ching-Yuan Yang, June-Ming Hsu and Shen-Iuan Liu, A 900-MHz/1-V CMOS frequency synthesizer, IEEE Journal of Solid-State Circuits, SC-35, pp. 1211-1214, Aug. 2000. (NSC89-2215-E-002-024)

78. Guang-Kaai Dehng, June-Ming Hsu, Ching-Yuan Yang, and Shen-Iuan Liu, Clock-deskew buffer using a SAR-controlled delay-locked loop, IEEE Journal of Solid-State Circuits, SC-35, pp. 1128-1136, Aug. 2000. (NSC89-2215-E-002-024)

77. Guo-Ming Sung, Jian-Fan Wei and Shen-Iuan Liu, Three types of 2-D lateral magneto-resistive sensors with P+-implant confinement, IEE Proceedings-Circuits Devices and Systems, vol. 147, pp. 158-164, June 2000.

76. Shen-Iuan Liu, Chien-Hung Kuo, Ruey-Yuan Tasi and Jingshown Wu, A double sampling pseudo-2-path bandpass delta-sigma modulator, IEEE Journal of Solid-State Circuits, pp. 276-280, Feb. 2000. (NSC87-2215-E002-027)

75. Weihsing Liu, Cheng-Chieh Chang, and Shen-Iuan Liu, Realization of exponential V-I converter using composite NMOS transistors, Electronics Letters, Vol. 36, pp. 8-10, Jan. 2000.

74. Jiin-Long Lee and Shen-Iuan Liu, Dual-input RC integrator and differentiator with tunable time constants using current-feedback amplifiers, Electronics Letters, Vol. 35, pp. 1910-1911, Oct. 1999.

73. Shen-Iuan Liu, Jiin-Long Lee and, Cheng-Chieh Chang, Low-voltage BiCMOS four-quadrant multiplier and squarer, Journal of Analog Integrated Circuits and Signal Processing, pp. 25-29, July 1999. (NSC85-2215-E-002-021)

72. Shen-Iuan Liu, Jiin-Long Lee and Cheng-Chieh Chang, Low-voltage BiCMOS four-quadrant multiplier using triode-region transistors, IEEE Trans. Circuits and Systems-I: Fundamental Theory and Applications, vol. 46, pp. 861-864, July 1999. (NSC85-2215-E-002-021)

71. Shen-Iuan Liu, Jian-Fan Wei and Guo-Ming Sung, Spice Macro model for MAGFET and its applications, IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 46, pp. 370-375, April 1999.

70. Shen-Iuan Liu, Jiunn-Hwa Lee and Hen-Wai Tsao, Low-power clock-deskew buffer for high-speed digital circuits, IEEE Journal of Solid-State Circuits, SC-34, pp. 554-558, April 1999.

69. Cheng-Chieh Chang and Shen-Iuan Liu, Analogue BiCMOS squarer and its applications, Electronics Letters, vol. 35, pp. 361-363, March 1999. (NSC88-2219-E-002-010)

68. Ching-Yuan Yang, Guang-Kaai Dehng, June-Ming Hsu and Shen-Iuan Liu, New dynamic filp-flops for high-speed dual modulus prescaler, IEEE Journal of Solid-State Circuits, SC-33, pp. 1568-1571, Oct. 1998. (NSC86-2622-E002-027)

67. Cheng-Chieh Chang and Shen-Iuan Liu, Weak inversion four-quadrant multiplier and two-quadrant divider, Electronics Letters, vol. 22, pp. 2079-2080, Oct. 1998. (NSC87-2218-E-002-016)

66. Shen-Iuan Liu and Ching-Yuan Yang, High input impedance filters using FTFNs, Int. Journal of Electronics, vol. 84, pp. 595-598, June 1998.

65. Jiann-Jong Chen, Shen-Iuan Liu and Yuh-Shyan Hwang, Low-voltage single power supply four-quadrant multiplier using floating-gate MOSFETs, IEE Proceedings-Circuits Devices and Systems, vol. 145, pp. 40-43, Feb. 1998.

64. Ching-Yuan Yang, Guang-Kaai Dehng and Shen-Iuan Liu, High-speed divide-by-4/5 counter for a dual modulus prescaler, Electronics Letters, vol. 33, pp. 1691-1692, Sept. 1997. (NSC85-2622-E012-019)

63. Shen-Iuan Liu, Single-Resistance-Controlled Sinusoidal Oscillator Using Two FTFNs, Electronics Letters, vol. 33, pp. 1185-1186, July 1997. (NSC85-2622-E012-019)

62. Shen-Iuan Liu and Chorng-Sii Hwang, Realization of Current-Mode Filters Using Single FTFN, Int. J. Electronics, vol. 82, pp. 499-502, May 1997.

61. PoKi Chen, Shen-Iuan Liu and Jingshown Wu, Highly accurate cyclic CMOS time-to-digital converter with extermely low power consumption, Electronics Letters, vol. 33, pp. 858-860, May 1997. (NSC85-2215-E-012-019)

60. Shen-Iuan Liu and Jiin-Long Lee, Voltage-mode universal filters using two current conveyors, Int. J. of Electronics, vol. 82, pp. 145-149, Feb. 1997.

59. Shen-Iuan Liu and Cheng-Chieh Chang, Low-voltage CMOS four-quadrant multiplier, Electronics Letters, vol. 33, pp. 207-208, Jan. 1997. (NSC86-2221-E-002-056)

58.Shen-Iuan Liu and Ching-Yuan Yang, Higher-Order Immittance Function Synthesis Using CCIIIs, Electronics Letters, vol. 32, pp. 2295-2296, Dec. 1996.

57. Shen-Iuan Liu and PoKi Chen, Low-Voltage CMOS Subthreshold Four-Quadrant Tripler, Journal of Analog Integrated Circuits and Signal Processing, vol. 11, pp. 303-307, Nov. 1996. (NSC85-2215-E-002-021)

56. Shen-Iuan Liu and Yu-Hung Liao, Table-Based Log-domain Linear Transformation Filter, Electronics Letters, vol. 32, pp. 1771-1772, Sept. 1996.

55. Shen-Iuan Liu and Yu-Hung Liao, Current-Mode Quadrature Sinusoidal Oscillator Using Single FTFN, Int. J. Electronics, vol. 81, pp. 171-175, Aug. 1996.

54. Shen-Iuan Liu, and Cheng-Chieh Chang, A CMOS Square-Law Vector Summation Circuit, IEEE Trans. on Circuits and Systems Pt. II, pp. 520-523, July 1996. (NSC83-0404-E-001-024 NSC84-2215-E-002-039)

53. Jiann-Horng Tsay, Shen-Iuan Liu, and Yan-Pei Wu, A simple and accurate method to measure the threshold voltage of a MOSFET using an MOS active attenuator, Int. J. Electronics, vol. 81, pp. 49-58, July 1996.

52. Shen-Iuan Liu, and Jiin-Long Lee, Insensitive Current-/Voltage-Mode Filters Using FTFNs, Electronics Letters, vol. 32, pp. 1079-1080, June 1996.

51. Shen-Iuan Liu and Cheng-Chieh Chang, Low-Voltage CMOS Four-Quadrant Multiplier Based On Square-Difference Identity, IEE Proceedings-Circuits, Devices and Systems, vol. 143, pp. 174-176, June 1996. (NSC85-2215-E-002-021)

50. Shen-Iuan Liu and Jiann-Horng Tsay, Single-resistance-controlled sinusoidal oscillator using current-feedback amplifiers, Int. J. Electronics, vol. 80, no. 5, pp. 661-664, May 1996.

49. Shen-Iuan Liu, Cheng-Chieh Chang and Yuh-Shyan Hwang, CMOS square-law four-quadrant multiplier and square circuits, Journal of Analog Integrated Circuits and Signal Processing, vol. 9, no. 3, pp. 257-264, April 1996. (NSC83-0404-E-001-024 NSC84-2215-E-002-039)

48. Wenwei Chiu, Shen-Iuan Liu, Hen-Wai Tsao and Jiann-Jong Chen, CMOS differential difference current conveyors and their applications, IEEE Proceedings-Circuits, Devices and Systems, vol. 143, pp. 91-96, April 1996.

47. Shen-Iuan Liu and Dah-Jiun Wei, Analogue squarer and Multiplier Based On MOS Square-Law Characteristic, Electronics Letters, vol. 32, pp. 541-542, March 1996. (NSC85-2215-E-002-021)

46. Shen-Iuan Liu, Cascadable Current-Mode Filters Using Single FTFN, Electronics Letters, vol. 31, pp. 1965-1966, Nov. 1995.

45. Yuh-Shyan Hwang, Shen-Iuan Liu, Dong-Shiuh Wu, and Yan-Pei Wu, Linear transformation all-pole filters based on current conveyors, Int. Journal of Electronics, vol. 79, pp. 439-445, Oct. 1995.

44. Wenwei Chiu, Jiann-Horng Tsay, Shen-Iuan Liu, Hen-Wai Tsao, and Jiann-Jong Chen, Single-capacitor MOSFET-C integrator using OTRA, Electronics Letters, vol. 31, pp. 1796-1797, Oct. 1995.

43. Shen-Iuan Liu, and Cheng-Chieh Chang, CMOS four-quadrant multiplier using active attenuators, Int. Journal of Electronics, vol. 79, pp. 323-328, Sept. 1995. (NSC83-0404-E-001-024 NSC84-2215-E-002-039)

42. Shen-Iuan Liu and Cheng-Chieh Chang, CMOS analog divider and four-quadrant multiplier using pool circuits, IEEE J. Solid-State Circuits, SC-30, pp. 1025-1029, Sept. 1995. (NSC83-0404-E-001-024 NSC84-2215-E-002-039)

41. Yuh-Shyan Hwang, Wenwei Chiu, Shen-Iuan Liu, Dong-Shiuh Wu, and Yan-Pei Wu, High-frequency linear transformation elliptic filters employing minimal OTAs, Electronics Letters, vol. 31, pp. 1562-1564, Aug. 1995.

40. Shen-Iuan Liu, Square-rooting and vector summation circuits using current conveyors, IEE Proceedings-Circuits, Devices and Systems, vol. 142, pp. 223-226, Aug. 1995.

39. Shen-Iuan Liu, and Dong-Shiuh Wu, New Current-Feedback Amplifier-Based Universal Biquadratic Filters, IEEE Trans. on Instrumentation and Measurement, IM-44, pp. 915-917, Aug. 1995.

38. Shen-Iuan Liu, Jiann-Jong Chen and Yuh-Shyan Hwang, New current-mode biquad filters using current followers, IEEE Trans. on Circuits and Systems, Pt. I : Fundamental Theory and Applications, CASI-42, pp. 380-383, July 1995.

37. Jiann-Jong Chen, Hen-Wai Tsao, Shen-Iuan Liu, and Wenwei Chiu, Parasitic-capacitance-insensitive current-mode filters using operational transresistance amplifiers, IEE Proceedings-Circuits, Devices and Systems, vol. 142, pp. 186-192, June 1995.

36. Shen-Iuan Liu, High input impedance filters with low component spread using current-feedback amplifiers, Electronics Letters, vol. 31, pp. 1042-1043, June 1995.

35. Jiann-Horng Tsay, Shen-Iuan Liu, and Yan-Pei Wu, CMOS four-quadrant multiplier using triode transistors based on regulated cascode structure, Electronics Letters, vol. 31, pp. 962-963, June 1995.

34. Dong-Shiuh Wu, Shen-Iuan Liu, Yuh-Shyan Hwang, and Yan-Pei Wu, Multiple-phase sinusoidal oscillator using CCIIs, Int. J. Electronics, vol. 78, No. 4, pp. 645-651, April 1995.

33. Shen-Iuan Liu, Universal filter using two current-feedback amplifiers, Electronics Letters, vol. 31, pp. 629-630, April 1995.

32. Shen-Iuan Liu, Single-resistance-controlled/voltage-controlled oscillators using current conveyors and grounded capacitors, Electronics Letters, vol. 31, pp. 337-338, March 1995.

31. Shen-Iuan Liu, and Cheng-Chieh Chang, CMOS subthreshold four-quadrant multiplier based on unbalanced source-coupled pairs, Int. J. Electronics, vol. 78, No. 2, pp. 327-332, Feb. 1995. (NSC83-0404-E-001-024 NSC84-2215-E-002-039)

30. Shen-Iuan Liu, and Yuh-Shyan Hwang, CMOS squarer and four-quadrant multiplier, IEEE Trans. on Circuits and Systems, Pt. I : Fundamental Theory and Applications, pp. 119-122, Feb. 1995. (NSC83-0404-E-001-024 NSC84-2215-E-002-039)

29. Shen-Iuan Liu, and Jiann-Jong Chen, Realisation of analogue divider using current feedback amplifiers, IEE Proceedings-Circuits, Devices and Systems, vol. 142, pp. 45-48, Feb. 1995.

28. Dong-Shiuh Wu, Shen-Iuan Liu, Yuh-Shyan Hwang, and Yan-Pei Wu, Multiphase sinusoidal oscillator using the CFOA pole, IEE Proceedings-Circuits, Devices and Systems, vol. 142, pp. 37-40, Feb. 1995.

27. Shen-Iuan Liu, Cheng-Chieh Chang, and Dong-Shiuh Wu, Active-R Sinusoidal Oscillators using the CFA pole, Int. J. Electronics, vol. 77, No. 6, pp. 1035-1042, Dec. 1994.

26. Shen-Iuan Liu, Chung-Shinn Shiuh and Dong-Shiuh Wu, Sinusoidal Oscillators with single element control using a current feedback amplifier, Int. J. Electronics, vol. 77, No. 6, pp. 1007-1013, Dec. 1994.

25. Shen-Iuan Liu, Low voltage CMOS four-quadrant multiplier, Electronics Letters, vol. 30, pp. 2125-2126, Dec. 1994. (NSC83-0404-E-001-024 NSC84-2215-E-002-039)

24. Yuh-Shyan Hwang, Shen-Iuan Liu, Dong-Shiuh Wu, and Yan-Pei Wu, Table-based linear transformation filters using OTA-C Techniques, Electronics Letters, vol. 30, pp. 2021-2022, Nov. 1994.

23. Shen-Iuan Liu, and Yuh-Shyan Hwang, Dual-input differentiators and integrators with tunable time constants using current conveyors, IEEE Trans. on Instrumentation and Measurement, IM-43, pp. 650-654, Aug. 1994.

22. Shen-Iuan Liu, and Yuh-Shyan Hwang, CMOS four quadrant multiplier using bias feedback techniques, IEEE Journal of Solid-State Circuits, SC-29, pp. 750-752, June 1994.

21. Dong-Shiuh Wu, Yuh-Shyan Hwang, Shen-Iuan Liu, and Yan-Pei Wu, New multi-function filter using an inverting CCII and a voltage follower, Electronics Letters, vol. 30, pp. 551-552, March 1994.

20. Shen-Iuan Liu, and Yuh-Shyan Hwang, Realisation of R-L and C-D impedances using a current feedback amplifier and its applications, Electronics Letters, vol. 30, pp. 380-381, March 1994.

19. Shen-Iuan Liu, and Yuh-Shyan Hwang, CMOS four-quadrant multiplier using bias-offset crosscoupled pairs, Electronics Letters, vol. 29, No. 20, pp. 1737-1738, Sept. 1993.

18. Shen-Iuan Liu, Jiann-Jong Chen, Hen-Wai Tsao, and Jiann-Horng Tsay, Design of Biquad Filters with a Single Current Follower, IEE Proceedings-G, vol. 140, no. 3, pp. 165-170, June 1993.

17. Shen-Iuan Liu, Dong-Shiuh Wu, Hen-Wai Tsao, Jingshown Wu, and Jiann-Horng Tsay, Nonlinear Circuit Applications with Current Conveyors, IEE Proceedings-G, vol. 140, pp. 1-6, Feb. 1993.

16. Shen-Iuan Liu, Yuh-Shyan Hwang, and Jiann-Horng Tsay, CCII-based fuzzy membership function and Max/Min circuits, Electronics Letters, vol. 29, pp. 116-118, Jan. 1993.

15. Shen-Iuan Liu, Jiann-Horng Kuo, and Jiann-Horng Tsay, New CCII-based current-mode biquadratic filters International Journal of Electronics, vol.72, pp. 243-252, Feb. 1992.

14. Chun-Chieh Chen, Jiann-Jong Chen, Hen-Wai Taso, and Shen-Iuan Liu, Euler differentiator with reduced channel length modulation, Electronics Letters, vol. 28, no. 42, pp. 419-420, Feb. 1992.

13. Jiann-Jong Chen, Chun-Chieh Chen, Hen-Wai Tsao, and Shen-Iuan Liu, Current mode oscillators using single current follower, Electronics Letters, vol. 27, no. 22, pp. 2056-2059, Oct. 1991.

12. Shen-Iuan Liu, Jiann-Horng Kuo, Hen-Wai Tsao, Jingshown Wu, and Jiann-Horng Tsay, New CCII-based differentiator and its applications, International Journal of Electronics , vol. 71, no. 4, pp. 645-652, Oct. 1991.

11. Chun-Li Hou,Yen-Pei Wu, and Shen-Iuan Liu, New configuration for single-CCII first-order and biquadratic current-mode filters, International Journal of Electronics, vol. 71, no. 4, pp. 637-644, Oct. 1991.

10. Shen-Iuan Liu, Jiann-Jong Chen, Jiann-Horng Tsay, New insensitive notch and allpass filters with single current follower, Electronics Letters vol. 27, no.19, pp. 1712-1713, Sept. 1991.

9. Shen-Iuan Liu, Jyh-Shyan Wang, Hen-Wai Tsao, and Jingshown Wu, TOCA-based electronically-tunable continuous-time filters, International Journal of Electronics, vol. 71, no. 2, pp. 253-264, Aug. 1991.

8. Shen-Iuan Liu, Chih-Hsien Chen, Hen-Wai Tsao, and Jingshown Wu, Switched- Current Differentiator-Based IIR and FIR Filters, International Journal of Electronics, vol. 71, pp. 81-91, July 1991.

7. Shen-Iuan Liu , Hen-Wai Tsao, Jingshown Wu, Ming Ou-Yang, and Jiann-Horng Tsay, New CMOS NIC-based MOSFET-C Filters, Electronics Letters, vol. 27, No.9, pp. 772-774, April 1991.

6. Shen-Iuan Liu and Hen-Wai Tsao, The Single CCII Biquads with High Input Impedance, IEEE Trans. on Circuits Systems, vol. 38, No. 4, pp. 456-461, April 1991.

5. Shen-Iuan Liu, Hen-Wai Tsao, and Jingshown Wu, CCII based Continuous-Time Filters with Reduced Gain-Bandwidth Sensitivity, IEE Proceedings-G, vol.138, No.2, pp. 210-216, April 1991.

4. Shen-Iuan Liu and Hen-Wai Tsao, New Configurations for Single CCII Biquads, International Journal of Electronics, vol. 70, No. 3, pp. 609-622, March 1991.

3. Shen-Iuan Liu, Hen-Wai Tsao and Jingshown Wu, Cascadable Current-Mode Single CCII Biquads, Electronics Letters, vol. 26, pp. 2005-2006, Nov. 1990.

2. Shen-Iuan Liu, Hen-Wai Tsao, Jingshown Wu, and Tung-Kwan Lin, MOSFET-Capacitor Filters Using Unity-Gain CMOS Current Conveyors, Electronics Letters, vol. 26, pp. 1430-1431, Aug. 1990.

1. Shen-Iuan Liu, Hen-Wai Tsao, and Jingshown Wu, Electronically Programmable MOSFET-C Filter, International Journal of Electronics, vol. 68, pp. 793-802, May 1990.

(B). Local and international Conferences

174. Hsi-Kai Peng and Shen-Iuan Liu, бзA 20-Gb/s jitter-tolerance-enhanced baud-rate CDR circuit with one-tap DFEби, accepted by 2024 VLSI Symposium on Technology, Systems and Applications

173. Yuan-Pang Huang and Shen-Iuan Liu, бзA 48-Gb/s baud-rate PAM-4 receiver with one-tap speculative DFE and reused comparatorsби, accepted by 2024 VLSI Symposium on Technology, Systems and Applications

172. Po-Yuan Chou and Shen-Iuan Liu, бзA 14.7-20-Gb/s reference-less baud-rate CDR circuit with one-tap DFE and time-interpolationби,accepted by 2024 VLSI Symposium on Technology, Systems and Applications

171.Yao-Hung Tsai, and Shen-Iuan Liu, бзA 0.0072-mm2 10-bit 100-MS/s calibration-free SAR ADC using digital place-and-route tools in 40-nm CMOSби, 2023 VLSI Symposium on Technology, Systems and Applications, pp. 106-109, April 2023.

170.Yi-En Hsu, and Shen-Iuan Liu, бзA 7~10.5-Gb/s reference-less linear half-rate CDR circuit using automatic band selectorби, 2023 VLSI Symposium on Technology, Systems and Applications, pp. 70-73, April 2023.

169.Yen-Min Tseng, Yu-Chi Yen, and Shen-Iuan Liu, бзAn injection-locked clock multiplier with injection strength calibrationби, International Symposium on VLSI Design, Automation & Test, Taiwan, pp. 27-30, April 2022.

168.Zhi-Heng Kang, Yu-Chi Yen, Guan-Yu Su, and Shen-Iuan Liu, бзAn adaptive digital PLL based on BBPFD transition probabilityби, International Symposium on VLSI Design, Automation & Test, Taiwan, pp. 23-26, April 2022.

167.Yen-Min Tseng, Yu-Chi Yen, and Shen-Iuan Liu, бзA digital phase-locked loop with background supply noise cancellationби, International Symposium on VLSI Design, Automation & Test, Taiwan, pp. 28-31, April 2021.

166.Guan-Yu Su, Zhi-Heng Kang, and Shen-Iuan Liu, бзAn adaptive loop gain tracking digital PLL using spectrum-balancing techniqueби, International Symposium on VLSI Design, Automation & Test, Taiwan, pp. 24-27, April 2021.

165.Ming-Chia Chang, Min-Hsuan Wu, and Shen-Iuan Liu, "A 500nW-50гgW indoor photovoltaic energy harvester with multi-mode MPPT", International Symposium on VLSI Design, Automation & Test, Taiwan, D6-1, Aug. 2020.

164.Yuan Cheng Qian, Yen-Yu Chao, and Shen-Iuan Liu, "A sub-sampling PLL with robust operation under supply interference and short re-locking time", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 95-98, Nov. 2019.

163.Ye-Sing Luo, Hsing-Hung Lin, and Shen-Iuan Liu, "A 13.56 MHz 88.7%-PCE voltage doubling rectifier using adaptive delay time and pulse-width control", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 39-42, Nov. 2018.

162.S. L. Lee, J. Chen, S.I. Liu, C. F. Yang, H. W. Tsao, S. H. Hsu, C. C. Lin, C. L. Yang, Z. J. Zhang, K. L. Fu. L. W. Chung, T. Pankra, "Development of 400 Gb/s optical transceivers for SMF based datacenter optical interconnect", 2018 27th Wireless and Optical Communication Conference (WOCC), pp. 1-4, April 2018.

161.Kuan-Lin Fu and Shen-Iuan Liu, "A 56Gbps PAM-4 optical receiver front-end", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 77-80, Nov. 2017.

160. Chi-Huan Chiang, Chang-Cheng Huang, Ting-Kuei Kuan, and Shen-Iuan Liu, "A digital MDLL using switched biasing technique to reduce low-frequency phase noise", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 101-104, Nov. 2016.

159. Chang-Cheng Huang, Kuo-Wei Tseng, and Shen-Iuan Liu, "A 10-20 Gb/s CDR circuit with 6200ppm frequency tracking", 2016 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) pp. 1-3, Aug. 2016.

158. Che-Wei Yeh, Cheng-En Hsieh, and Shen-Iuan Liu, "A 3.2GHz digital phase-locked loop with background supply noise cancellation", International Solid-State Circuits Conference (ISSCC), pp. 332-334, Feb. 2016.

157. Chi-Huan Chiang, Chang-Cheng Huang and Shen-Iuan Liu, "A digital bang-bang phase-locked loop with bandwidth calibration", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 13-4, Nov. 2015.

156. Ting-Kuei Kuan and Shen-Iuan Liu, "A digital bang-bang phase-locked loop with automatic loop gain control and loop latency reduction", 2015 Symposium on VLSI Circuits, pp. C9-2, June 2015.

155. Ting-Kuei Kuan, Yu-Hsuan Chiang, and Shen-Iuan Liu, "A 0.43pJ/bit true random number generator", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 33-36, Nov. 2014.

154. Chien-Kai Kao, Kuan-Lin Fu, and Shen-Iuan Liu, "A 2X25 Gb/s clock and data recovery with background amplitude-locked loop", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 281-284, Nov. 2014

153. Yuan-Fu Lin, Chang-Cheng Huang, Jiunn-Yih Max Lee, Chih-Tien Chang, and Shen-Iuan Liu, "A 5-20 Gb/s power scalable adaptive linear equalizer using edge counting", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 273-276, Nov. 2014

152. Cheng-En Hsieh and Shen-Iuan Liu, "A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18гgm CMOS", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 325-328, Nov. 2014.

151. Ye-Sing Luo and Shen-Iuan Liu, "A low-input-swing AC-DC voltage multiplier using Schottky diodes", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 245-248, Nov. 2014.

150. Ye-Sing Luo, Jiun-Ru Wang, Wei-Jen Huang, Je-Yu Tsai, I-Chin Wu, Yi-Fang Liao, Wan-Ting Tseng, Chen-Tung Yen, Pai-Chi Li, and Shen-Iuan Liu, "Ultrasonic telemetry and neural stimulator with FSK-PWM signaling", International Symposium on VLSI Design, Automation & Test, Taiwan, pp. 136-139, April 2013.

149. I-Ting Lee, Yen-Jen Chen, Shen-Iuan Liu, Chewn-Pu Jou, Fu-Lung Hsueh, and Hsieh-Hung Hsieh, "A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing", International Solid-State Circuits Conference (ISSCC), pp. 414-415, Feb. 2013.

148. Yu-Ming Ying, I-Ting Lee and Shen-Iuan Liu, "A 20Gb/s adaptive duobinary transceiver", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 129-132, Nov. 2012.

147. I-Ting Lee, Yun-Ta Tsai and Shen-Iuan Liu, "A fast-locking phase-locked loop using CP control and gated VCO", International Symposium on VLSI Design, Automation & Test, Taiwan, pp. 1-4, April 2012.

146. Yi-Chieh Huang and Shen-Iuan Liu, "A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing", International Solid-State Circuits Conference (ISSCC), pp. 338-339, Feb. 2012.

145. Liang-Hsin Chen, Min-Han Hsieh, Shen-Iuan Liu, and Charlie Chung-Ping Chen, " A 6.7 MHz-to-1.24 GHz 0.0318 mm2 fast-locking all-digital DLL in 90 nm CMOS", International Solid-State Circuits Conference (ISSCC), pp. 244-245, Feb. 2012.

144. I-Ting Lee, Yun-Ta Tsai, and Shen-Iuan Liu, "A leakage-current-recycling phase-locked loop in 65nm CMOS technology", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 137-140, Nov. 2011.

143. I-Ting Lee, Chiao-Hsing Wang, and Shen-Iuan Liu, "3.6mW D-band divide-by-3 injection-locked frequency dividers in 65nm CMOS", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 93-96, Nov. 2011.

142. Chang-Lin Hsieh and Shen-Iuan Liu, "A 40Gb/s adaptive receiver with linear equalizer and merged DFE/CDR", 2011 Symposium on VLSI Circuits, pp. 208-209, June 2011.

141. Yi-Chieh Huang and Shen-Iuan Liu, "A 6Gb/s receiver with 32.7dB adaptive DFE-IIR equalization", International Solid-State Circuits Conference (ISSCC) 2011, pp. 356-357, Feb. 2011.

140. Yu-Ming Ying and Shen-Iuan Liu, "A 20Gb/s digitally adaptive equalizer/DFE with blind sampling", International Solid-State Circuits Conference (ISSCC) 2011, pp. 444-445, Feb. 2011.

139. Bo-Yu Lin, I-Ting Lee, Chiao-Hsing Wang, and Shen-Iuan Liu, "A 198.9GHz ~201.0GHz injection-locked frequency divider in 65nm CMOS", 2010 Symposium on VLSI Circuits, pp. 49-50, June 2010.

138. Chao-Ching Hung, and Shen-Iuan Liu, "A 35.56GHz all-digital phase-locked loop with high resolution varactors", International Symposium on VLSI Design, Automation & Test, Taiwan,pp. 245-248, April 2010.

137. Chao-Ching Hung, I-Fong Chen, and Shen-Iuan Liu, "A 1.25GHz fast-locked all-digital phase-locked loop with supply noise suppression", International Symposium on VLSI Design, Automation & Test, Taiwan, pp. 237-240, April 2010.

136. I-Hsin Wang, and Shen-Iuan Liu, "An integrating analog-to-digital data converter with variable resolution", International Symposium on VLSI Design, Automation & Test, Taiwan, pp. 186-189, April 2010.

135. I-Fong Chen, Rong-Jyi Yang, and Shen-Iuan Liu, "Loop latency reduction technique for all-digital clock and data recovery circuits", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 309-312, Nov. 2009.

134. Wei-Ming Lin, Kuang-Fu Teng, and Shen-Iuan Liu, "A delay-locked loop with digital background calibration", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 317-320, Nov. 2009.

133. Wei-Ming Lin, Chan-Fei Lin, and Shen-Iuan Liu, "A CBSC second-order sigma-delta modulator in 3um LTPS-TFT Technology", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 113-116, Nov. 2009.

132. Hong-Lin Chu, Chang-Lin Hsieh and Shen-Iuan Liu, "A 10Gb/s inductorless quarter-rate clock and data recovery circuit in 0.13um CMOS", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 165-168, Nov. 2009.

131. Chang-Lin Hsieh, and Shen-Iuan Liu, "A 40Gb/s decision feedback equalizer using back-gate feedback technique", 2009 Symposium on VLSI Circuits, pp. 218-219, June 2009.

130. Bo-Yu Lin, and Shen-Iuan Liu, "A 132.7-to-143.5GHz injection-locked frequency divider in 65nm CMOS", 2009 Symposium on VLSI Circuits, pp. 230-231, June 2009.

129. Hwei-Yu Lee and Shen-Iuan Liu, "A 140MS/s 10-bit Pipelined ADC with a Folded S/H Stage", 2009 IEEE International Symposium on Circuits and Systems (ISCAS 2009), pp. 976-979, May 2009.

128. Wei-Ming Lin, Chao-Chyun Chen, and Shen-Iuan Liu, "An all-digital clock generator for dynamic frequency scaling", International Symposium on VLSI Design, Automation & Test, Taiwan, pp. 251-254, April 2009.

127. Jung-Yu Chang, Che-Wei Fan, and Shen-Iuan Liu, "A frequency synthesizer for mode-1 MB-OFDM UWB applications", International Symposium on VLSI Design, Automation & Test, Taiwan, pp. 219-222, April 2009.

126. Wei-Jen Huang, Chein-Lung Chen, and Shen-Iuan Liu, "A wireless power telemetry with self-calibrated resonant frequency", International Symposium on VLSI Design, Automation & Test, Taiwan, pp. 80-83, April 2009.

125. Kun-Hung Tsai, and Shen-Iuan Liu, "A 43.7mW 96GHz phase-locked loop in 65nm CMOS technology", International Solid-State Circuits Conference (ISSCC), pp. 276-277, Feb. 2009.

124. Bo-Yu Lin, Kun-Hung Tsai, and Shen-Iuan Liu, "A 128.24~137.00GHz injection-locked frequency divider in 65nm CMOS", International Solid-State Circuits Conference (ISSCC), pp. 282-283, Feb. 2009.

123. Chao-Ching Hung, and Shen-Iuan Liu, "A leakage-suppression technique for phase-locked systems in 65nm CMOS technology", International Solid-State Circuits Conference (ISSCC), pp. 400-401, Feb. 2009.

122. Hong-Lin Chu, Chaung-Lin Hsieh, and Shen-Iuan Liu, "20Gb/s 1/4-rate and 40Gb/s 1/8-rate burst-mode CDR circuits in 0.13гgm CMOS", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 429-433, Nov. 2008.

121. I-Hsin Wang and Shen-Iuan Liu, "A 4-bit 10GSample/sec flash ADC with merged interpolation and reference voltage", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 377-380, Nov. 2008.

120. Jung-Yu Chang, Chi-Nan Chuang, Shen-Iuan Liu, "A 15-20GHz delay-locked loop in 90nm CMOS technology", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 213-216, Nov. 2008.

119. Wei-Jen Huang and Shen-Iuan Liu, "A sub-1V low-dropout regulator with an on-chip voltage reference", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 165-168, Nov. 2008.

118. Chao-Ching Hung, Chihun Lee, Lan-Chou Cho, and Shen-Iuan Liu, "A 57.1-59GHz CMOS fractional-N frequency synthesizer using quantization noise shifting technique", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.413-416, Nov. 2008.

117. Ke-Hou Chen, Chihun Lee, and Shen-Iuan Liu, "A dual-band 61.4~63GHz/ 75.5~77.5GHz CMOS receiver in a 90nm technology", 2008 Symposium on VLSI Circuits, pp. 160-161, June 2008.

116. Lan-Chou Cho, Kun-Hung Tsai, Chao-Ching Hung, and Shen-Iuan Liu, "93.5~ 109.4GHz CMOS injection-locked frequency divider with 15.3% locking range", 2008 Symposium on VLSI Circuits, pp. 86-87, June 2008.

115. Jian-Hao Lu, Ke-Hou Chen, and Shen-Iuan Liu, "A 40Gb/s low-power analog equalizer in 0.13гgm CMOS technology", 2008 Symposium on VLSI Circuits, pp. 54-55, June 2008.

114. Jian-Hao Lu, Ke-Hou Chen, An-Ming Lee, Ting-Ying Wu, and Shen-Iuan Liu, "A merged CMOS digital near-end crosstalk canceller and analog equalizer for multi-lane serial-link receivers", 2008 Symposium on VLSI Circuits, pp. 56-57, June 2008.

113. Kun-Hung Tsai, Jia-Hao Wu, and Shen-Iuan Liu, "Frequency dividers with enhanced locking range", The 2008 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 661-663, June 2008.

112. Kun-Hung Tsai, Jia-Hao Wu, and Shen-Iuan Liu, "A digitally calibrated 64.3-66.2GHz phase-locked loop", The 2008 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 307-310, June 2008.

111. Ding-Shiuan Shen, Chao-Ching Hung, and Shen-Iuan Liu, "A 40GHz fractional-N frequency synthesizer in 0.13um CMOS", The 2008 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 295-299, June 2008.

110. Kun-Hung Tsai and Shen-Iuan Liu, "A 62-66.1GHz phase-locked loop in 0.13um technology", International Symposium on VLSI Design, Automation & Test, Taiwan, pp. 113-116, April 2008.

109. Kun-Hung Tsai, Lan-Chou Cho, Jia-Hao Wu and Shen-Iuan Liu, "3.5mW W-band frequency divider with wide locking range in 90-nm CMOS technology", International Solid-State Circuits Conference (ISSCC) 2008, pp. 466-467, Feb. 2008.

108. Chih-Fan Liao and Shen-Iuan Liu, "A 40-Gb/s CMOS serial-link receiver with adaptive equalization and CDR", International Solid-State Circuits Conference (ISSCC) 2008, pp. 100-101, Feb. 2008.

107. Che-Fu Liang and Shen-Iuan Liu, "A 20/10/5/2.5Gbps power-scaling burst-mode CDR circuit using GVCO/Div2/DFF tri-mode cells", International Solid-State Circuits Conference (ISSCC) 2008, pp. 224-225, Feb. 2008.

106. Hwei-Yu Lee, and Shen-Iuan Liu, "A 8-bit 140MS/s pipelined ADC using folded sample-and-hold stage", International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 357-360, Dec. 2007.

105. Shao-Ku Kao, and Shen-Iuan Liu, "A fast-locked all-digital delay-locked loop with non-50% input duty cycle", International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp.1125-1128, Dec. 2007.

104. Shao-Ku Kao, and Shen-Iuan Liu, "A wide-range all-digital duty cycle corrector with a period monitor", International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 349-352, Dec. 2007.

103. Kun-Hung Tsai and Shen-Iuan Liu, "A 39.2~45.5GHz frequency divider using a switched cross-coupled pair", International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 409-412, Dec. 2007.

102. Shao-Hung Lin, Chang-Lin Hsieh and Shen-Iuan Liu, "A half-rate bang-bang phase/frequency detector for continuous-rate CDR circuits", International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp.353-356, Dec. 2007.

101. Wei-Ming Lin and Shen-Iuan Liu, "An all-digital reused-SAR delay-locked loop with adjustable duty cycle", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 312-315, Nov. 2007.

100. Hong-Lin Chu and Shen-Iuan Liu, "A 10Gb/s burst-mode transimpedance amplifier in 0.13гgm CMOS", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 400-403, Nov. 2007.

99. Chao-Chyun Chen and Shen-Iuan Liu, "An infinite phase shift delay-locked loop with voltage-controlled sawtooth delay line", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 448-451, Nov. 2007.

98. Jian-Hao Lu, Chi-Lun Luo, and Shen-Iuan Liu, "A Passive Filter for 10-Gb/s Analog Equalizer in 0.18-гgm CMOS Technology", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 404-407, Nov. 2007.

97. Hwei-Yu Lee, I-Hsin Wang, and Shen-Iuan Liu, "A 7-bit 400MS/s sub-ranging flash ADC in 0.18um CMOS", IEEE International SOC Conference, pp. 11-14, Sept. 2007.

96. Hwei-Yu Lee and Shen-Iuan Liu, "A 10-bit 100MS/s pipelined ADC in 0.18гgm CMOS technology", IEEE International SOC Conference, pp. 3-6, Sept. 2007.

95. Ke-Hou Chen, Jian-Hao Lu and Shen-Iuan Liu, "A 2.4GHz efficiency-enhanced rectifier for wireless telemetry", IEEE Custom Integrated Circuits Conference, pp. 555-558, Sept. 2007.

94. Che-Fu Liang, Sy-Chyuan Hwu and Shen-Iuan Liu, "A jitter-tolerance-enhanced CDR using a GDCO-based phase detector", 2007 Symposium on VLSI Circuits, pp. 274-275, June 2007.

93. Jung-Yu Chang and Shen-Iuan Liu, "A 4-54GHz static frequency divider with back-gate coupling", International Symposium on VLSI Design, Automation & Test, Taiwan, pp. 212-215, April 2007.

92. I-Hsin Wang and Shen-Iuan Liu, "A 1V 5-bit 5GSample/sec CMOS ADC for UWB receivers", International Symposium on VLSI Design, Automation & Test, Taiwan, pp. 140-143, April 2007.

91. I-Hsin Wang and Shen-Iuan Liu, "A 4-bit, 13.5GSample/sec track-and-hold circuit", International Symposium on VLSI Design, Automation & Test, Taiwan, pp. 144-147, April 2007.

90. Chihun Lee and Shen-Iuan Liu, "A 58-to-60.4GHz frequency synthesizer in 90nm CMOS", International Solid-State Circuits Conference (ISSCC) 2007, pp.196-197, Feb. 2007.

89. Chi-Nan Chuang and Shen-Iuan Liu, "A 40GHz DLL-based clock generator in 90nm CMOS technology", International Solid-State Circuits Conference (ISSCC) 2007, pp.178-179, Feb. 2007.

88. Chih-Fan Liao and Shen-Iuan Liu, "A 40Gb/s Transimpedance-AGC amplifier with 19dB DR in 90nm CMOS", International Solid-State Circuits Conference (ISSCC) 2007, pp.54-55, Feb. 2007.

87. Lan-Chou Cho, Chihun Lee and Shen-Iuan Liu, "A 33.6-to-33.8Gb/s burst-mode CDR in 90nm CMOS", International Solid-State Circuits Conference (ISSCC) 2007, pp.48-49, Feb. 2007.

86. Rong-Jyi Yang, and Shen-Iuan Liu, "A 2.5GHz, 30mW, 0.03mm2, all-digital delay-locked loop", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 271-274, Nov. 2006.

85. Che-Fu Liang, Sy-Chyuan Hwu and Shen-Iuan Liu, "A 10Gbps burst-mode CDR circuit in 0.18гgm CMOS", IEEE Custom Integrated Circuits Conference, pp. 599-602, Sept. 2006.

84. Chihun Lee, Lan-Chou Cho and Shen-Iuan Liu, "A 44GHz dual-modulus divide-by-4/5 prescaler in 90nm CMOS technology", IEEE Custom Integrated Circuits Conference, pp. 397-400, Sept. 2006.

83. Chao-Chyun Chen, Sheng-Chou Lee, and Shen-Iuan Liu, "A capacitor multiplication technique using a second-generation current conveyor", 17th VLSI Design/CAD Symposium, Taiwan, Session B3, Aug. 2006.

82. Yen-Horng Chen, Chih-Wei Wang, Ching-Feng Lee, Jen-Lung Liu, Tzu-Yi Yang, Chih-Fan Liao, Che-Fu Liang, Gin-Kou Ma, Shen-Iuan Liu, "A 0.18гgm CMOS receiver for 3.1 to 10.6GHz MB-OFDM UWB communication systems", 2006 RFIC Symposium, RMO4B-1, pp. 297-300, June 2006.

81. Chihun Lee, Lan-Cho Chou and Shen-Iuan Liu, Chun-Lin Ko, Ying-Zong Juang, Chin-Fong Chiu, "A 1.2V 37-38.5GHz 8-phase clock generator in 0.13um CMOS technology", 2006 Symposium on VLSI Circuits, pp. 34-35, June 2006.

80. Chihun Lee and Shen-Iuan Liu, "A 35-Gb/s limiting amplifier in 0.13um CMOS technology", 2006 Symposium on VLSI Circuits, pp. 152-153, June 2006.

79. Jian-Hao Lu, Chi-Lun Luo, and Shen-Iuan Liu, "An adaptive 3.125Gbps coaxial cable equalizer", International Symposium on VLSI Design, Automation & Test, Taiwan, pp. 219-222, April 2006.

78. Bo-Jiun Chen, Shao-Ku Kao, and Shen-Iuan Liu, "An all-digital duty cycle corrector", International Symposium on VLSI Design, Automation & Test, Taiwan, pp. 195-198, April 2006.

77. Wei-Jen Huang, Sao-Hung Lu, and Shen-Iuan Liu,"A capacitor-free CMOS low dropout regulator with slew rate enhancement", International Symposium on VLSI Design, Automation & Test, Taiwan, pp. 211-214, April 2006.

76. Chao-Chyun Chen, Sheng-Chou Lee and Shen-Iuan Liu, "A fully integrated spread spectrum clock generator", International Symposium on VLSI Design, Automation & Test, Taiwan, pp. 191-194, April 2006.

75. Che-Fu Liang, Shen-Iuan Liu, Yen-Horng Chen, Tzu-Yi Yang and Gin-Kou Ma, "A 14-band frequency synthesizer for MB-OFDM UWB application", International Solid-State Circuits Conference (ISSCC) 2006, pp. 126-127, Feb. 2006.

74. Chih-Fan Liao and Shen-Iuan Liu, "A 10Gb/s CMOS automatic gain control amplifier with 35dB dynamic range for 10Gigabit Ethernet", International Solid-State Circuits Conference (ISSCC) 2006, pp. 516-517, Feb. 2006.

73. I-Hsin Wang, Wei-Sheng Chen, and Shen-Iuan Liu, "A 5Gbps CMOS automatic gain control amplifier for 10GBase-LX", Proceedings of Technical Papers on IEEE Asian Solid-State Circuits, pp. 169-172, Nov. 2005.

72. Jung-Yu Chang, Chia-Hsin Wu, and Shen-Iuan Liu, "A low-phase-noise low-phase-error 2.4GHz CMOS quadrature VCO", Proceedings of Technical Papers on IEEE Asian Solid-State Circuits, pp. 281-284, Nov. 2005.

71. Che-Fu Liang, Shih-Tsai Liu, Hsiang-Hui Chang, and Shen-Iuan Liu, "A calibrated pulse generator for impulse-radio UWB applications", Proceedings of Technical Papers on IEEE Asian Solid-State Circuits, pp. 293-296, Nov. 2005.

70. Che-Fu Liang and Shen-Iuan Liu, "A fast-switching frequency synthesizer for UWB applications", Proceedings of Technical Papers on IEEE Asian Solid-State Circuits, pp. 197-200, Nov. 2005.

69. Che-Fu Liang, Sy-Chyuan Hwu, and Shen-Iuan Liu, "A 2.5Gbps burst-mode clock and data recovery circuit", Proceedings of Technical Papers on IEEE Asian Solid-State Circuits, pp. 457-460, Nov. 2005.

68. Chihun Lee, Lan-Chou Cho, and Shen-Iuan Liu, "A 0.1-25.5-GHz differential cascaded-distributed amplifier in 0.18-гgm CMOS Technology", Proceedings of Technical Papers on IEEE Asian Solid-State Circuits, pp. 129-132, Nov. 2005.

67. Tysh-Bin Liu, Wei-Jen Huang, and Shen-Iuan Liu, "A dual-phase digital PWM controller for DC-DC switching converters with current balancing", Proceedings of Technical Papers on IEEE Asian Solid-State Circuits, pp. 161-164, Nov. 2005.

66. Sao-Hung Lu, Wei-Jen Huang, and Shen-Iuan Liu, "A fast settling low dropout linear regulator with single Miller compensation capacitor", Proceedings of Technical Papers on IEEE Asian Solid-State Circuits, pp. 153-156, Nov. 2005.

65. Chih-Fan Liao and Shen-Iuan Liu, "A broadband noise-canceling CMOS LNA for 3.1бV10.6-GHz UWB receiver", IEEE Custom Integrated Circuits Conference, pp. 161 - 164, Sept. 2005.

64. Chao-Chyun Chen, Sheng-Chou Lee, and Shen-Iuan Liu, "A spread-spectrum clock generator using a capacitor multiplication technique", The 5th Emerging Information Technology Conference (EITC 2005), Taiwan, Aug. 2005.

63. Hung-Chun Chen, Jung-Yu Chang, and Shen-Iuan Liu, "A 3.125-Gb/s laser driver for 10GBase-LX4 Ethernet", 2005 VLSI/CAD Symposium, Taiwan, Poster Session P2, Aug. 2005.

62. Chao-Chyun Chen, Sheng-Chou Lee, and Shen-Iuan Liu, "Cycle slipping reduction technique in phase-locked loops", 2005 VLSI/CAD Symposium, Taiwan, Session B3, Aug. 2005.

61. Chien-Hung Kuo, Chang-Hung Chen, Huang-Shih Shen-Iuan Liu,"A tunable bandpass DS modulator using double sampling", IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3676-3679, May 2005.

60. Hua-Chin Lee, Chien-Chih Lin, Chia-Hsin Wu, Shen-Iuan Liu, Chorng-Kuang Wang and Hen-Wai Tsao, "A 15mW 69dB 2Gsamples/s CMOS analog front-end for low-band UWB applications", IEEE International Symposium on Circuits and Systems (ISCAS), pp. 368-371, May 2005.

59. Hua-Chin Lee, Chien-Chih Lin, Chia-Hsin Wu, Shen-Iuan Liu, Chorng-Kuang Wang, and Hen-Wai Tsao, "CMOS Low-Band UWB Analog Front-End", 2004 VLSI/CAD Symposium, Taiwan, P4-19, Aug. 2004.

58. Jung-Yu Chang, and Shen-Iuan Liu, "An AC-coupled Quadrature LC tank VCO", 2004 VLSI/CAD Symposium, Taiwan, B2-1, Aug. 2004.

57. Chun-Yi Kuo, Che-Fu Liang, and Shen-Iuan Liu, "A 5.8-/5.2-/2.4-GHz SiGe LC VCO with Wide Tuning Range", 2004 VLSI/CAD Symposium, Taiwan, B2-2, Aug. 2004.

56. I-Hsin Wang, Chung-Shun Liu, and Shen-Iuan Liu, "A low power 5Gb/s transimpedance amplifier with dual feedback technique", AP-ASIC 2004, Session 14-6, pp. 304-307, Aug. 2004.

55. Rong-Jyi Yang and Shen-Iuan Liu, "A 1.7~3.125Gbps clock and data recovery circuit using a gated frequency detector", AP-ASIC 2004, Session 14-5, pp. 326-329, Aug. 2004.

54. Chihun Lee, Chia-Hsin Wu, and Shen-Iuan Liu, "A 1.2V 18mW 10Gb/s SiGe transimpedance amplifier", AP-ASIC 2004, Session 14-5, pp. 300-303, Aug. 2004.

53. Chia-Hsin Wu, Jieh-Wei Liao, and Shen-Iuan Liu, "A 1V 4.2mW Fully Integrated 2.5Gb/s CMOS Limiting Amplifier using Folded Active Inductors", International Symposium on Circuits and Systems (ISCAS), Vol. I, pp. 1044-1047, May 2004.

52. Chia-Hsin Wu, Chang-Shun Liu, and Shen-Iuan Liu, "A 2GHz CMOS Variable-Gain Amplifier with 50dB Linear-in-Magnitude Controlled Gain Range for ProjectsBase-LX4 Ethernet", International Solid-State Circuits Conference (ISSCC) 2004, pp. 484-485, Feb 2004.

51. Hsiang-Hui Chang, Shang-Ping Chen, Shen-Iuan Liu, "A Shifted-Averaging VCO with Precise Multiphase Outputs and Low Jitter Operation", 29th European Solid-State Circuits Conference, CP17, Sept. 2003.

50. Hsiang-Hui Chang, Chih-Hao Sun, and Shen-Iuan Liu, "Low Jitter Butterworth Delay-Locked Loops", 2003 Symposium on VLSI Circuits, pp.177-180, June 2003.

49. Chia-Hsin Wu, Chun-Yi Kuo, and Shen-Iuan Liu "Selective Metal Parallel Shunting Inductor and Its VCO Application", 2003 Symposium on VLSI Circuits, pp.37-40,June 2003.

48. Hsiang-Hui Chang, Chih-Hao Sun, and Shen-Iuan Liu, "A Low Jitter and Precise Multiphase Delay-Locked Loop Using Shifted Averaging VCDL ", International Solid-State Circuits Conference (ISSCC), pp. 434-435, Feb. 2003.

47. Chien-Hung Kuo, Tsung-Kai Kao, and Shen-Iuan Liu, "A 1V, 11-Bits Double-Sampling Delta-Sigma Modulator", 2003 VLSI/CAD, Taiwan, pp. 201-204, Aug. 2003.

46. Chia-Hsin Wu, Jieh-Wei Liao, Chih-Hun Lee, and Shen-Iuan Liu, "A 1V 4.2mW Fully Integrated 2.5Gb/s CMOS Limiting Amplifier using Folded Active Inductors", 2003 VLSI/CAD, Taiwan, pp. 49-52, Aug. 2003.

45. Chia-Hsin Wu,Chih-Chun Tang, and Shen-Iuan Liu, Image rejection relaxed 5GHz CMOS receiver front-end, 2002 VLSI/CAD, Taiwan, pp. 47-50, Aug. 2002.

44. Rong-Jyi Yang, Ming-Zhe Liu and Shen-Iuan Liu, Gigahertz CMOS monolithic frequency synthesizer, 2002 VLSI/CAD, Taiwan, pp. 232-235, Aug. 2002.

43. Lan-Cho Chou, Chih-Hao Sun, and Shen-Iuan Liu, Low-jitter DLLs with the butterworth characteristics, 2002 VLSI/CAD, Taiwan, pp. 252-255, Aug. 2002.

42. Hsiang-Hui Chang, Shang-Ping Chen, Kuang-Wei Cheng and Shen-Iuan Liu, A 0.8V switched-opamp bandpass delta sigma modulator using a two-path architecture, 2002 IEEE ASIA-PACIFIC Conference on ASIC, pp. 1-4, Aug. 2002.

41. Chia-Hsin Wu,Chih-Chun Tang, and Shen-Iuan Liu, Analysis of on-chip spiral inductors using distributed capacitance model, 2002 IEEE ASIA-PACIFIC Conference on ASIC, pp. 259-262, Aug. 2002.

40. Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang and Shen-Iuan Liu, A wide-range and fixed latency of one clock cycle delay-lock looped loop, IEEE ISCAS 2002, vol. III, pp. 675-678, May 2002.

39. Chia-Hsin Wu,Chih-Chun Tang, and Shen-Iuan Liu, Analysis and application of miniature 3D inductor, IEEE ISCAS 2002, vol. II, pp. 811-814, May 2002.

38. Chih-Chun Tang, and Shen-Iuan Liu, CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90-degree delay network, IEEE ISCAS 2002, vol. III, pp. 77-80, May 2002.

37. Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang and Shen-Iuan Liu, A Wide-range and Fixed Latency of One Clock Cycle Delay-Lock Looped Loop IEEE CICC 2002, pp. 49-52, May 2002.

36. Chih-Chun Tang and Shen-Iuan Liu, A 1V 5.8GHz CMOS Low Noise Amplifier in a 0.35um CMOS Process, accepted by 2001 International Symposium on Communications, Tainan, Taiwan, Nov. 2001.

35. Chih-Chun Tang, Chia-Hsin Wu, Chi-Kun Chiu, Shen-Iuan Liu, Analysis and Application of Miniature 3D Inductor, 12 th VLSI Design/CAD Symposium, Taiwan, R.O.C., Session: RF ICs, Sensors and Actuators, B3-1, Aug. 2001.

34. Shr-Lung Chen, Hsiang-Hui Chang, Kun-Hsien Li, Shen-Iuan Liu, CMOS Magnetic to Digital Converter Using DS Oversampling Modulator, 12 th VLSI Design/CAD Symposium, Taiwan, R.O.C., Session: RF ICs, Sensors and Actuators, B3-4, Aug. 2001.

33. Chia-Hsin Wu, Chih-Chun Tang, Shen-Iuan Liu, A 2.4GHz CMOS LNA with New Area-Efficient Inductor, 12 th VLSI Design/CAD Symposium, Taiwan, R.O.C., Session: RF ICs, Sensors and Actuators, B3-10, Aug. 2001.

32. Giang-Kaai Dehng, Jyh-Woei Lin and Shen-Iuan Liu, A Fast-lock Mixed-mode DLL Using a 2-b SAR Algorithm, IEEE Custom Integrated Circuits Conference, pp. 489-492, May 2001.

31. Chih-Chun Tang, Wen-Shih Lu, Lan-Da Van, Wu-Shiung Feng and Shen-Iuan Liu, A 2.4-GHz CMOS Down-Conversion Doubly Balanced Mixer with Low Supply Voltage, the International Symposium on Circuits and Systems (ISCAS), Sydney, Vol. IV, pp. 749-797, May 2001.

30. Lee-An Ho , Shr-Lung Chen , Chien-Hung Kuo, and Shen-Iuan Liu, CMOS Oversampling Delta-Sigma Magnetic to Digital Converters, IEEE International Symposium on Circuits and Systems (ISCAS), Sydney, Vol. I, pp. 388-391, May 2001.

29. Jian-Ming Yang, Chi-Kun Chiu, and Shen-Iuan Liu, A 2.4GHz CMOS LC-Tank Voltage-Controlled Oscillator, the 11th VLSI/CAD symposium, Taiwan, R.O.C., pp. 269-272, Aug. 2000.

28. Yu-Shun Huang, Chia-Shin Wu, and Shen-Iuan Liu, 2.4-GHz CMOS RF Front-End Receiving Circuits, the 11th VLSI/CAD symposium, Taiwan, R.O.C., pp. 261-264 , Aug. 2000. (one of the two best student paper awards)

27. Chorng-Sii Hwang, Wang-Chih Chung, Chih-Yung Wang, C. Wang, Hen-Wai Tsao and Shen-Iuan Liu, A 2V Clock Synchronizer using Digital Delay-Locked Loop, AP-ASIC, Korea, pp. 91-94 Aug. 2000.

26. Guang-Kaai Dehng, Wei-Hung Chen, Jong-Woei Chen and Shen-Iuan Liu, A CMOS 455 Mbps/channel LVDS Receiver for Flat Panel Display, the 10th VLSI/CAD symposium, Taiwan, R.O.C., pp. 365-368, Aug. 1999.

25. Guang-Kaai Dehng, Jong-Woei Chen, Wei-Hung Chen and Shen-Iuan Liu, High Speed CMOS Interface Circuits for IEEE-1394 High Performance Serial Bus, the 10th VLSI/CAD symposium, Taiwan, R.O.C., pp. 221-222, Aug. 1999.

24. PoKi Chen and Shen-Iuan Liu, A cyclic CMOS time-to-digital converter with deep subnanosecond resolution, Proceedings of IEEE Custom Integarted Circuits Conference, pp. 605-608, May 1999. (NSC87-2215-E-002-027)

23. Guang-Kaai Dehng and Shen-Iuan Liu, A 750MHz/1V 128/129 prescaler using a voltage doubler, 1999 International analog VLSI workshop, pp. 57-61, May 1999.

22. June-Ming Hsu, Shen-Iuan Liu, Ching-Yuan Yang and Guang-Kaai Dehng, A 1V CMOS dynamice back-gate forward bias prescaler for frequency synthesizer application, 1999 International analog VLSI workshop, pp. 45-50, May 1999.

21. Ching-Yuan Yang, June-Ming Hsu and Shen-Iuan Liu, A 4GHz CMOS dual modulus prescaler with high speed dynamic flip-flops, the 9th VLSI/CAD symposium, Taiwan, R.O.C., pp. 203-206, Aug. 1998.

20. Guang-Kaai Dehng and Shen-Iuan Liu, A 1.4GHz 1/128 dynamic frequency divider using standard Si CMOS technology, the 9th VLSI/CAD symposium, Taiwan, R.O.C., pp. 199-202, Aug. 1998.

19. Jian-Fan Wei, Guo-Ming Sung and Shen-Iuan Liu, Spice Macro model for MAGFET and its applications, ▓─дGйбй`ж╠дu╡{иt▓╬з▐│Nму░Q╖|, pp. 147-152, May 1998.

18. Ching-Yuan Yang, W. C. Chung and Shen-Iuan Liu, Efficiently reduced pull-in time of PLL with nonlinear phase comparator, the 8th VLSI/CAD symposium, Taiwan, R.O.C., pp. 205-208, Aug. 1997. (NSC85-2622-E012-019)

17. Chia-Ling Wei, Hen-Wai Tsao and Shen-Iuan Liu, Design and realization of harmonic mixer, the 8th VLSI/CAD symposium, Taiwan, R.O.C., pp. 209-212, Aug. 1997. (NSC85-2262-E002-021)

16. Shen-Iuan Liu, Tzong-Bang Yu and Hen-Wai Tsao, Pipeline Direct Digital Frequency Synthesizer without Sine ROM Table, the 8th VLSI/CAD symposium, Taiwan, R.O.C., pp. 161-164, Aug. 1997. (NSC86-2215-E-002-038)

15. Jiann-Jong Chen, Shen-Iuan Liu and Yuh-Shyan Hwang, Low-voltage single power supply four-quadrant multiplier using floating-gate MOSFETs, IEEE Proceedings of ISCAS'97, pp. 237-240, 1997.

14. PoKi Chen, Shen-Iuan Liu and Jingshown Wu, A Low Power High Accuracy CMOS Time-to-Digital Converter, IEEE Proceedings of ISCAS'97, pp. 281-284, 1997.

13. Shen-Iuan Liu, PoKi Chen, Chin-Yang Chen and Jenn-Gwo Hwu, Analog Maximum, Median and Minimum Circuit, IEEE Proceedings of ISCAS'97, pp. 257-260, 1997.

12. Ching-Liang Dai, Pei-Zen Chang, Shui-Shong Lu, Dah-Jian Wei and Shen-Iuan Liu, An integrated capacitive micro accelerometer using standard CMOS process, International Electronic Devices and Material Symposium, HsinChu, Taiwan, E3-4-P.315, Dec. 1996.

11. Chen-Chun Lai, Lung-Jieh Yang, Pei-Zen Chang, Ching-Liang Dai, Dah-Jian Wei and Shen-Iuan Liu, A pizeoresistive pressure sensor fabricated by a commercial DPDM CMOS process, International Electronic Devices and Material Symposium, HsinChu, Taiwan, E3-2-P.307, Dec. 1996.

10. Shen-Iuan Liu , Chih-Feng Lin, and Ching-Yuan Yang, A PLL-Based Programmable Clock Generator with 15 to 180-MHz Lock Range, the 7th VLSI/CAD symposium, Taiwan, R.O.C., pp. 151-154, Aug. 1996.

9. Yang-Han Lee, Hui-I Cheng, Hao-Chang Chang, Chun-ChengChen and Shen-Iuan Liu, Digital IF FSK demodulator for pager receiver, Proceedings of the IASTED/ISMM International Conference on Modeling and Simulations, pp. 50-53, April 1996.

8. Jiann-Horng Tsay, Shen-Iuan Liu, Yan-Pei Wu, Measuring the threshold voltage of a MOSFET with an active attenuator, IEEE Proceedings of ISCAS '96, pp. 397-400, 1996.

7. Shen-Iuan Liu, PoKi Chen and Jiann-Horng Tsay, Wide Range Linear Tunable BiCMOS Transconductor and Multiplier, IEEE Proceedings of ISCAS '96, pp. 308-311, 1996.

6. Shen-Iuan Liu, Chih-Hsien Chen, Hen-Wai Tsao and Jingshown Wu, Realization of IIR and FIR Filters Using Switched-Current Differentiators, IEEE ICCAS '91 on China, pp. 688-691, June 1991.

5. Shen-Iuan Liu, Chih-Hsien Chen, Hen-Wai Tsao and Jingshown Wu, Switched- Current Modified Bilinear Integrator and its Filter Applications, IEEE Proceedings of ISCAS '91, pp. 1805-1808, June 1991.

4. Shen-Iuan Liu, Hen-Wai Tsao, Jingshown Wu, and Jiann-Horng Tsay, Realization of the Single CCII Biquads with High Input Impedance, IEEE Proceedings of ISCAS '91, pp.1428-1431, June 1991.

3. Shen-Iuan Liu, Hen-Wai Tsao, and Jingshown Wu, New Configurations for Single CCII Biquads, 1990 International Electron Devices and Material Symposium, R.O.C., pp. 358-361, Nov. 1990.

2. Shen-Iuan Liu, Hen-Wai Tsao, Jingshown Wu, Tsai-Chung Yu, and Tung-Kwan Lin, Design and Optimization of MOSFET-Capacitor Filters Using CMOS Current Conveyors, IEEE Proceedings of ISCAS '90, pp. 2283-2286, May 1990.

1. Shen-Iuan Liu and Jyou-Min Shyu, Optimization-Based Design for Continuous-Time MOSFET-Capacitor Filters 1989 International Electron Devices and Material Symposium, R.O.C., pp. 398-401, 1989.

(C). Articles

1. │╒дh╜╫дх, "The analysis and design of the current-mode circuits", Department of Electrical Engineering, National Taiwan University, Jan. 1991.

2. ▒i░Ўдп,зf╛╟дh,╝B▓`▓W,╖и└sкN,"йT║Aе[│tл╫нp┬▓д╢",╣qдlдыеZе|ды╕╣, pp. 59-62, April 1996.

3. └╣и}╝y,▒i░Ўдп,╝B▓`▓W,"CMOS╖L╖P┤·╛╣дз│]нp╗P╗s│y",мь╗Ў╖sк╛▓─дQдKиўдT┤┴ ,pp. 49-58, Dec. 1996.

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(D). Patents

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├■зO	▒MзQжW║┘	░ъзO	▒MзQ╕╣╜X	╡oй·дH	▒MзQ┼vдH	▒MзQ┤┴╢б	░ъмь╖\|нp╡e╜s╕╣
A1	дм╕╔жбкўоёеb╣qмy╣B┐щ╛╣д╬иф┬oкi╛╣└│е╬	дд╡╪е┴░ъ	55,527	╝B▓`▓W зd└R╢п ▒флэ░╢	дuму░\| ╣qдlй╥	81/04/01~ 96/03/31	б@
A2	CMOS current conveyor and its filter applications	м№░ъ	5,124,666	╝B▓`▓W зd└R╢п ▒флэ░╢	дuму░\| ╣qдlй╥	81/06/23~ 98/06/22	б@
A3	ец┤л╣qмy╖Lд└╛╣д╬иф┬oкi╛╣└│е╬	дд╡╪е┴░ъ	59,072	╝B▓`▓W зd└R╢п ▒флэ░╢	дuму░\| ╣qдlй╥	81/10/21~ 96/10/20	б@
A4	Switched-current differentiator and its filter applications	м№░ъ	5,097,155	╝B▓`▓W зd└R╢п ▒флэ░╢	дuму░\| ╣qдlй╥	81/03/17~ 98/03/16	б@
A5	дм╕╔жбкўоёеbзC╣q└ге\|╢Hннн╝кk╛╣	дд╡╪е┴░ъ	72,138	╝B▓`▓W	░ъмь╖\|	84/07/01~ 104/7/8	NSC83-0404-E-001-024&NSC84-2215-E-002-039
A6	е\|╢Hннн╝кk╛╣	дд╡╪е┴░ъ	74,211	╝B▓`▓W	░ъмь╖\|	84/10/21~ 104/5/15	NSC83-0404-E-001-024&NSC84-2215-E-002-039
A7	Four-Quadrant Multiplier	м№░ъ	5,557,228	╝B▓`▓W	░ъмь╖\|	84/10/21~ 104/5/15	NSC83-0404-E-001-024&NSC84-2215-E-002-039
A8	жV╢qйM╕╦╕m	дд╡╪е┴░ъ	76,707	╝B▓`▓W	░ъмь╖\|	85/02/21~ 104/5/29	NSC83-0404-E-001-024&NSC84-2215-E-002-039
A9	Vector Summation Device	м№░ъ	5,506,538	╝B▓`▓W	░ъмь╖\|	85/04/09~ 104/5/4	NSC83-0404-E-001-024&NSC84-2215-E-002-039
A10	дм╕╔жбкўоёеb┬∙оt░╩╣qмy╣B┐щ╛╣д╬иф└│е╬дз┐nд└╣q╕ЇйM┬oкi╣q╕Ї	дд╡╪е┴░ъ	79,061	╝B▓`▓W	░ъмь╖\|	85/06/21~ 104/2/22	NSC83-0404-E-001-024&NSC84-2215-E-002-039
A11	зQе╬░╛└гж^и№з▐│Nдзкўоёеbе\|╢Hннн╝кk	дд╡╪е┴░ъ	79,959	╝B▓`▓W зd└R╢п	░ъмь╖\|	85/07/21~ 104/1/18	NSC83-0417-E-002-004
A12	Differential-difference current conveyor applications	м№░ъ	5,596,289	╝B▓`▓W	░ъмь╖\|	85/01/21~ 104/5/15	NSC83-0404-E-001-024&NSC84-2215-E-002-039
A13	зQе╬кўоёеb╣q┤╣┼щйє╣бйM░╧дзендшл▀пSй╩дзкўоёеbе\|╢Hннн╝кk╛╣╗Pендш╛╣	дд╡╪е┴░ъ	80932	╝B▓`▓W зd└R╢п ╢└и\|╜х	░ъмь╖\|	85/09/01~ 104/01/18	NSC83-0417-E-002-004
A14	Four-Quadrant Three-Input Multiplier	м№░ъ	5,602,504	╝B▓`▓W	░ъмь╖\|	86/02/11~ 104/9/15	NSC83-0404-E-001-024&NSC84-2215-E-002-039
A15	CMOS Low-voltage Four-Quadrant Multiplier	м№░ъ	5,656,964	╝B▓`▓W	░ъмь╖\|	86/8/12~ 104/7/26	NSC83-0404-E-001-024&NSC84-2215-E-002-039
A16	к╜▒╡╝╞жь└W▓vжXжи╛╣	дд╡╪е┴░ъ	96435	┤хйv║] ╝B▓`▓W ▒флэ░╢	░ъмь╖\|	87/08/11~ 106/10/01	NSC86-2215-E002-038
A17	лH╕╣│B▓z╕╦╕m	дд╡╪е┴░ъ	100449	│пзBй_ ╝B▓`▓W ▒флэ░╢ зd└R╢п	░ъмь╖\|	88/01/11~ 106/05/29	NSC85-2622-E-002-019
A18	Divide by 4/5 counter	м№░ъ	5930322	╖и▓M▓W ╝B▓`▓W	░ъмь╖\|	88/07/27~ 106/10/28	NSC85-2622-E-002-019
A19	├■дё▒╞з╟╗Pддн╚╣q╕Ї	дд╡╪е┴░ъ	102377	╝B▓`▓W ╢└и\|╜х	░ъмь╖\|	88/04/11~ 106/11/27	NSC85-2215-E-002-021
A20	Direct Digital Frequency Synthesizer	м№░ъ	5986483	┤хйv║] ╝B▓`▓W ▒флэ░╢	░ъмь╖\|	88/11/16~ 106/12/01	NSC86-2215-E002-038
A21	зC╣q└гдм╕╔жбкўоёеbдT┐щдJн╝кk╛╣	дд╡╪е┴░ъ	107570	╝B▓`▓W	░ъмь╖\|	88/09/11~ 104/08/14	NSC84-2215-E-002-039
A22	░к└Wдм╕╔жбкўоёеb┬∙╝╥/жh╝╥лe╕mд└└W╛╣	дд╡╪е┴░ъ	114359	╖и▓M▓W ╝B▓`▓W │пи}░Є	░ъмь╖\|	89/04/11~ 105/09/22	NSC85-2622-E-002-019
A23	░г4/5╣q╕Ї	дд╡╪е┴░ъ	107136	╖и▓M▓W ╝B▓`▓W	░ъмь╖\|	88/08/21~ 106/10/01	NSC85-2622-E-002-019
A24	┬∙н┐и·╝╦║[╡ъ└└дT│q╕Ї▒a│q┐nд└дTид╜╒┼▄╛╣	дд╡╪е┴░ъ	115348	╜▓╖чнь ╝B▓`▓W зd└R╢п	░ъмь╖\|	89/05/21~ 107/11/04	NSC87-2215-E-002-027
A25	лH╕╣│B▓z╕╦╕m	м№░ъ	6118390	│пзBй_ ╝B▓`▓W ▒флэ░╢ зd└R╢п	░ъмь╖\|	89/09/12~ 106/10/10	NSC85-2622-E-002-019
A26	┬∙н┐и·╝╦║[╡ъ└└дT│q╕Ї▒a│q┐nд└дTид╜╒┼▄╛╣	м№░ъ	6172631B1	╜▓╖чнь ╝B▓`▓W зd└R╢п	░ъмь╖\|	90/01/09~ 108/02/01	NSC87-2215-E-002-027
A27	зC╣q└гиуйш╕╔╣q└г╕╔└vдзд┴┤л╣qоe┐nд└╛╣д╬┬oкi╛╣	м№░ъ	6169440B1	╝B▓`▓W	░ъмь╖\|	90/01/02~ 108/06/26	NSC87-2218-E-002-016
A28	░к└Wдм╕╔жбкўоёеb┬∙╝╥/жh╝╥лe╕mд└└W╛╣	м№░ъ	6094466	╖и▓M▓W ╝B▓`▓W │пи}░Є	░ъмь╖\|	89/07/25~ 106/01/10	NSC85-2622-E-002-019

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