-
[2011/02/01] Please check
your
final grades and contact Prof. Jiang by email at
jhjiang@cc.ee.ntu.edu.tw
if there is any problem. Also please drop by Prof. Jiang's office in
Room 242, EE2 Building on 2/8 Tuesday 14:00-17:00 if needed. Note that the grades will be sent
to the university on 2/9 noon and NO changes can be made afterwards.
-
[2011/01/24] All the updated
scores (without project) are
summarized.
-
[2011/01/24] The TAs will
hold an office hour in Room 229, EE2 Building from 15:00 to 17:00 Tue
(1/25). Please drop by for grading questions.
-
[2011/01/23] Please check
your HW3,
and updated HW4
scores and contact TA 馮紹惟同學 if there is any problem.
-
[2011/01/22] Please check
your updated HW5,
and HW6 scores and contact TA 馮紹惟同學 if
there is any problem. (HW3 will be announced soon, and HW4 scores
will be updated soon.)
-
[2011/01/21] Please check
your HW7 scores and contact TA 馮紹惟同學 if
there is any problem. (HW3 will be announced soon, and HW4, 5, 6 scores
will be updated soon.)
-
[2011/01/17] Please see HW5
solution explanation by TA 白炳川同學.
-
[2011/01/13] Please check
your HW4, HW5,
and HW6 scores and contact TA 馮紹惟同學 if
there is any problem. (HW3 and HW7 will be announced soon.)
-
[2011/01/13] Reminder about
report submission:
Deadline: 2011/01/17 17:00
Please submit your hardcopy
report and a CD including all electronic files to Prof. Jiang's
office (Room 242, EE2) or mailbox in EE2 building by the deadline.
Refer to prior
project announcement for detailed
requirements.
-
[2011/01/13] Please check the
following lab absence list and contact TA 馮紹惟同學 if there is any problem:
09/24 Lab 1 (Verilog):
R98943008, R98943137
10/01 Lab 2 (Verilog):
R99943122, R98943008
10/29 Lab 3 (Synthesis):
R98943008, R98943150, R98943164, D94943007
11/05 Lab 4 (DFT): R98943008,
R98943012, D97943037, D94943007, R98943148
11/19 Lab 5 (STA): D99943009,
R97943150, R99943122, R98943008, R98943009, R98943012, R98943039,
D94943007, R98943148
11/26 Lab 6 (P&R): D99943009,
R98943173, D98943034, R98943008, R98943012, R97943162, D94943007,
R98943148
12/03 Lab 7 (P&R): D99943009,
R99943122, D98943034, R98943008, R98943012, R98943039, R98943132,
R98943145, R97943162, D94943007, R98943148
12/10 Lab 8 (DRC): D99943009,
R99943122, R99943145, R98943008, R98943009, R98943012,
R98943039, R98943145, R96943134, D94943004, R97943162,
D94943007, R98943148
12/17 Lab 9 (Verification):
D94943004, D94943007, R98943148, D97943037, R97943161, R97943162,
R98943010, R98943012, R98943173, R99921068, R99943115
12/24 Lab 10 (FPGA):
D99943009, R98943008, R98943009, R98943039, R98943145, R96943134,
D99943009, R98943008, R98943009, R98943039, R98943145, R96943134,
D94943004, D94943007, R98943148, R97943161, R97943162, R98943010,
R98943012, R99921068, D99943011, R98943132, R99943029, R99943145,
R99943159
-
[2010/12/23] The presentation
schedule is announced.
-
[2010/12/17] For project
presentation, your presence is mandatory for peer-review evaluation. The
presentation schedule will be announced soon in early next week.
-
[2010/12/17] Please check
your Homework 2 score (updated 12/23) and contact TA if
there is any problem.
-
[2010/12/08] Instructions on
IO pad insertion was posted on the lecture
page, which may be helpful to HW7.
-
[2010/12/07] Please check
your midterm exam grades (paper,
computer). If you have any question,
please see TAs in Room 229, EE2 Building 18:00-20:00 on 12/9 (Thursday).
-
[2010/11/09] Homework 3 is
updated. (valid_o spec and timing diagram changed; online submission and
hardcopy report due notice)
-
[2010/11/02]
期中考注意事項.
-
[2010/10/29] Prior midterm
programming exams: 2009,
2008,
2007,
2006.
-
[2010/10/28] If your HW2
design failed synthesis, you may use the reference
design instead. In this case, you may get a degraded score.
-
[2010/10/27] Please check
your Homework 1 score and contact TA if
there is any problem.
-
[2010/10/21] 在執行ncsim的時候,
我們要看simulation的波形結果的話需要吐出.fsdb或者.vcd檔, 這兩個檔案都很大, 尤其是.vcd檔案. 這次作業二, 吐的是.fsdb檔. 不過只要沒有寫完成, 模擬就不會結束, 除非使用者強制中止(ctrl+c),
否則吐出來的波形檔就會越來越大.
以下有兩個建議: 1. ncsim吐波形出來會用掉不少硬碟空間, 所以跑ncsim一段時間後(以這次作業來看, 大概30秒就足夠了)若一直沒有結束, 要按ctrl+c強制中止,
才不會導致波形一直寫入硬碟空間. 2. 本來的testbench是要收到design吐出的訊號才會執行中止, 建議testbench要再加上一個條件,
就是跑超過幾個cycle就會中止(這個範圍可以大一點, 避免未做完模擬就停掉).
-
[2010/10/01] Please submit
your homework assignments online using ftp through
host IP:
140.112.175.123
port:
9527
username: cvsd_students
password: cvsd2010
- [2010/08/02] Please check back frequently to this page for announcements.
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