Switching Circuits and Logic Design


Fall 2014

Introduction Announcements Lectures Readings Administrations Links


Slides
Assignments




Date Notes / Slides Assignments Notes

09/18/2014

09/19/2014

(Preview held by TA)

(Preview held by TA)

 HW1 assigned §1~§2 (due 10/3 before lecture)

 

 (9/18, 9/19 Prof. Jiang out of country) 

09/25/2014

09/26/2014

§1 Introduction, Number Systems and Conversion (unit00, unit01)

§2 Boolean Algebra (unit02)

 

 

 9/25 additional makeup lecture (13:20-14:10 same room)

9/26 additional makeup lectures (17:30-18:20 same room)

10/02/2014

10/03/2014

§3 Boolean Algebra (Continued) (unit03)

§4 Applications of Boolean Algebra (unit04)

 HW2 assigned §3~§4 (due 10/17 before lecture)

 

  10/2 additional makeup lecture (13:20-14:10 same room)

10/09/2014

10/10/2014

§5 Karnaugh Maps (unit05)

National Day

 

 

 

10/16/2014

10/17/2014

§5 Karnaugh Maps

§7 Multi-Level Gate Circuits (unit07)

 HW3 assigned §5, §7 (due 10/31 before lecture)

 

 

10/23/2014

10/24/2014

Quiz 1 (§1~§4)

§7 Multi-Level Gate Circuits; §8 Combinational Circuit Design (skip §8.1 and §8.2)  (unit08)

   

10/30/2014

10/31/2014

§8 Combinational Circuit Design (skip §8.1 and §8.2)

§9 Multiplexers, Decoders, and Programmable Logic Devices (skip §9.7)  (unit09)

HW4 assigned §8~§9 (due 11/14 before exam)

 

10/30 additional makeup lecture (13:20-14:10 same room)  

11/06/2014

11/07/2014

(TA holds office hour in class)

Verilog: Combinational Circuits (held by TA)

    (11/6 Prof. Jiang out of country)

11/13/2014

11/14/2014

Discussion Session

Midterm Exam (§1~§9)

   

11/20/2014

11/21/2014

§11 Latches and Flip-Flops (unit11)

§11 Latches and Flip-Flops

   

11/27/2014

11/28/2014

§12 Registers and Counters (unit12)

§12 Registers and Counters

HW5 assigned §11~§12 (due 12/12 before lecture)

 

12/04/2014

12/05/2014

§13 Analysis of Clocked Sequential Circuits (unit13)

§13 (cont'd)

   

12/11/2014

12/12/2014

§14 Derivation of State Graphs and Tables (skip Examples 2, 3 of §14.3) (unit14)

§14 (cont'd);  §15 Reduction of State Tables (§15.1 ~ §15.2) (unit15)

HW6 assigned §13~§14 (due 12/26 before lecture)

 

 

12/18/2014

12/19/2014

Quiz 2 (§11~§13)

Verilog: Sequential Circuits (held by TA)

Project announced (due 1/5 Monday noon)

 

 

12/25/2014

12/26/2014

§16 Sequential Circuit Design (§16.1 ~ §16.4) (unit16)

§16 (cont'd)

HW7 assigned §15~§16 (due 1/9 before lecture)

 

 

01/01/2015

01/02/2015

Happy New Year!

Help Session

 

 

01/08/2015

01/09/2015

Presentation of Selected Projects

Supplementary Materials

   

01/15/2015

01/16/2015

Discussion Session

Final Exam

  final exam score announced (1/21)