(Copyright Notice) The copyright of the class lecture notes belongs to the instructor (Prof. Chung-Yang Huang). The instructor spends a lot of time and efforts in preparing the lecture notes (slides), so please respect his copyright. Any duplication or distribution of the lecture notes, either in soft or hard copy, without the authorization of the author is a violation of the copyright.

Topics

1. Class Overview; Administrative Information (slides 70KB)

2. SoC Design Overview (slides 612KB)

3. Verification Techniques Overview (I) (Simulation, Emulation, Formal Verification) (slides 670KB)

4. Verification Techniques Overview (II) (Static Analysis, Physical Verification, Testing) (revised slides 525KB)

5. Final Project Help Slides (Introduction to EDA tool implementation, SAT and BDD engines) (slides 151KB)

6. System-Level Design and Verification (slides 434KB)

7. Simulation-based Verification (revised slides 229KB)

DAC 2003 Accellera SystemVerilog Workshop

(0) Introduction: SystemVerilog Motivation (slides 286KB)

(1) SystemVerilog for Design: Language Tutorial (slides 238KB)

(2) SystemVerilog for Verification: Language Tutorial (slides 342KB)

(3) SystemVerilog Assertions: Language Tutorial (slides 205KB) Using SystemVerilog Assertions and Testbench Together (slides 137KB)

(4) SystemVerilog APIs (slides 211KB)

(5) SystemVerilog Momentum: Verilog2001 to SystemVerilog (slides 922KB)

- SystemVerilog 3.1a Language Reference Manual (4.15MB)

- SystemVerilog v.s SystemC (OSCII presentation) (120KB)

8. Formal Verification Techniques (I) (Circuit Modeling) (slides 94.8KB)

9. Formal Verification Techniques (II) (ATPG and SAT Basics) (slides 506KB) (NOTE: Update from 12/03/04 starts from pages 71)

10. Formal Verification Techniques (III) (Sequential Verification Techniques) (slides 380KB) (NOTE: Update on 12/31/04 starts from pages 43; based on the “Unbounded SAT slides”) (Unbounded SAT slides 400KB)