09/13/2012

09/14/2012

§1 Introduction, Number Systems and Conversion (unit00, unit01)

§2 Boolean Algebra (unit02)

09/20/2012

09/21/2012

§2 Boolean Algebra

§3 Boolean Algebra (Continued) (unit03)

HW1 assigned (due 10/4 before lecture)

09/27/2012

09/28/2012

§4 Applications of Boolean Algebra (unit04)

10/04/2012

10/05/2012

§5 Karnaugh Maps (unit05)

HW2 assigned (due 10/18 before lecture)

10/11/2012

10/12/2012

§7 Multi-Level Gate Circuits (unit07 slides 20, 22 updated on 10/11)

10/18/2012

10/19/2012

Quiz 1 (§1~§5)

§8 Combinational Circuit Design (skip §8.1 and §8.2)  (unit08)

10/25/2012

10/26/2012

§8 Combinational Circuit Design (skip §8.1 and §8.2)

§9 Multiplexers, Decoders, and Programmable Logic Devices (skip §9.7)  (unit09)

HW3 assigned (due 11/9 before lecture)

HW3 due right before midterm exam

11/01/2012

11/02/2012

§9 Multiplexers, Decoders, and Programmable Logic Devices (skip §9.7)

Verilog: Combinational Circuits (15:30~18:00, by TA) (material)

11/08/2012

11/09/2012

No Lecture

Midterm Exam (announcement)

11/15/2012

11/16/2012

University Anniversary (No Lecture)

§11 Latches and Flip-Flops (unit11)

11/22/2012

11/23/2012

§12 Registers and Counters (unit12)

HW4 assigned with Verilog lab questions (due 12/6 before lecture)

HW4 with lab problem set

11/29/2012

11/30/2012

§13 Analysis of Clocked Sequential Circuits (unit13)

12/06/2012

12/07/2012

§14 Derivation of State Graphs and Tables (skip Examples 2, 3 of §14.3) (unit14)

HW5 assigned (due 12/20 before lecture)

12/13/2012

12/14/2012

Quiz 2 (§11~§13)

§15 Reduction of State Tables (§15.1 ~ §15.2) (unit15)

12/20/2012

12/21/2012

§16 Sequential Circuit Design (§16.1 ~ §16.4) (unit16)

HW6 assigned (due 1/3 before lecture)

12/27/2012

12/28/2012

§18 Circuits for Arithmetic Operations (§18.1 ~ §18.2) (unit18)

01/03/2013

01/04/2013

Supplementary Materials

01/10/2013

01/11/2013

No Lecture

Final Exam