Publications
- ACM/IEEE Journal Papers:
- Y.-W. Chang, D. F. Wong, and C. K. Wong,
``Universal switch modules for FPGA design,''
ACM Trans. on Design Automation of Electronic Systems (TODAES),
Vol. 1, No. 1, pp. 80--101, January 1996.
(All-time top-4 most highly cited paper of TODAES; #2 among non-survey papers)
See an implementation report
for our universal switch modules
from Dept. of EECS, Univ. of California at Berkeley.
- S. Thakur, Y.-W. Chang, D. F. Wong, and S. Muthukrishnan,
``Algorithms for an FPGA switch module routing problem
with application to global routing,''
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD),
Vol. 16, No. 1, pp. 32--47, January 1997.
- G.-M. Wu and Y.-W. Chang,
"Quasi-universal switch matrices for FPD design,"
IEEE Trans. on Computers (TC),
Vol. 48, No. 10, pp. 1107-1122, Oct. 1999.
- M. Shyu, Y.-D. Chang, G.-M. Wu, and Y.-W. Chang,
"Generic universal switch blocks,"
IEEE Trans. on Computers (TC), vol. 49, no. 4,
pp. 348--359, April 2000.
- Y.-W. Chang, K. Zhu, and D. F. Wong,
``Timing-driven routing for symmetrical-array-based FPGAs,''
ACM Trans. on Design Automation of Electronic Systems,
Vol. 5, No. 3, pp. 433--450,
July 2000.
- H.-R. Jiang, Y.-W. Chang, and J.-Y. Jou,
"Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD),
Vol. 19, No. 9, pp. 999--1010, September 2000.
- Y.-W. Chang, J.-M. Lin, and D. F. Wong,
"A matching-based algorithm for FPGA channel segmentation design,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 20, No. 6, pp. 784--791, June 2001.
- G.-M. Wu, J.-M. Lin, and Y.-W. Chang,
``Generic ILP-based approaches for time-multiplexed FPGA partitioning,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 20, No. 10, pp. 1266--1274, October 2001.
- H. Fang, Y.-L. Wu, and Y.-W. Chang,
"Comments on "Generic universal switch blocks","
IEEE Trans. on Computers (TC), vol. 51, no.1, pp. 93--95, 2002.
- G.-M. Wu, J.-M. Lin, and Y.-W. Chang,
``Performance-driven placement for dynamically reconfigurable FPGAs,"
ACM Trans. on Design Automation of Electronic Systems, Vol. 7, No. 4, pp. 628--642, October 2002.
- J.-M. Lin, H.-L. Lin, and Y.-W. Chang,
``Arbitrarily shaped rectilinear module placement using the transitive closure graph representation,"
IEEE Trans. VLSI Systems, Vol. 10, No. 6, pp. 886--901, December 2002.
- Y.-W. Chang, K. Zhu, D. F. Wong, G.-M. Wu, and C. K. Wong,
``Analysis of FPGA/FPIC switch modules,''
in ACM Trans. on Design Automation of Electronic Systems, Vol. 8, No. 1, pp. 11-37, January 2003.
- G.-M. Wu, Y.-C. Chang, and Y.-W. Chang,
``Rectilinear block placement using B*-trees,"
ACM Trans. on Design Automation of Electronic Systems, Vol. 8., No. 2, pp. 188--202, April 2003. (Best Paper Nominee)
- J.-M. Lin, Y.-W. Chang, and S.-P. Lin, "Corner sequence: A P-admissible floorplan representation with a worst-case linear-time packing scheme,"
IEEE Trans. VLSI Systems, Vol. 11, No. 4, pp. 679--686, August 2003.
- T.-C. Chen, S.-R. Pan, and Y.-W. Chang,
``Timing modeling and optimization under the transmission line model,"
IEEE Trans. VLSI Systems, Vol. 12, No. 1, pp. 28--41, January 2004.
- Y.-W. Chang and S.-P. Lin,
"MR: A New Framework for Multilevel Full-Chip Routing,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 23, No. 5, pp. 793--800, May 2004.
- H.-R. Jiang, Y.-W. Chang, J.-Y. Jou, K.-Y. Chao,
``Simultaneous Floorplanning and Buffer Block Planning,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 23, No. 5, pp. 694--703, May 2004.
- J.-M. Lin and Y.-W. Chang,
``TCG-S: Orthogonal Coupling of P*-admissible Representations for General Floorplans,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 23, No. 6, pp. 968--980, June 2004.
- J.-M. Lin and Y.-W. Chang,
``TCG: A transitive closure graph based representation for general floorplans,"
IEEE Trans. VLSI Systems, Vol. 13, No. 2, pp. 288--292, February 2005.
- T.-Y. Ho, Y.-W. Chang, S.-J. Chen, and D. T. Lee,
"Crosstalk-and performance-driven multilevel full-chip routing,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 24, No. 6, pp. 869--878, June 2005.
- H.-R. Jiang, S.-R., Pan, Y.-W. Chang, and J.-Y. Jou,
``Reliable Crosstalk-driven interconnect optimization,"
ACM Trans. on Design Automation of Electronic Systems, Vol. 11, No. 1, January 2006.
- T.-C. Chen and Y.-W. Chang,
``Modern Floorplanning Based on B*-trees and Fast Simulated Annealing,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 4, pp. 637--650, April 2006.
- S.-W. Tu, J.-Y. Jou, and Y.-W. Chang,
``RLC coupling-aware simulation and on-chip bus encoding for delay reduction,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 10, pp. 2258--2264, October 2006.
- K. S.-M. Li, C.-C. Su, Y.-W. Chang, C.-L. Lee, and J. E Chen,
``P1500 Standard Compatible Interconnect Diagnosis for Delay and Crosstalk Faults,
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 11, pp. 2513--2525, November 2006.
- C.-W. Liu and Y.-W. Chang, "Power/ground network and
floorplan co-synthesis for fast design convergence,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, No. 4, pp. 693--704, April 2007.
- B.-Y. Su, Y.-W. Chang, and J. Hu,
``An exact jumper insertion algorithm for antenna violation avoidance/fixing considering routing obstacles,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, No. 4, pp. 719--734, April 2007.
- T.-C. Chen and Y.-W. Chang, "Multilevel full-chip gridless routing with applications to optical proximity correction," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, No. 6, pp. 1041--1053, June 2007.
- H.-C. Lee, Y.-W. Chang, and H. Yang,
``MB*-tree: A multilevel floorplanner for large-scale building-module design,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, No. 8, pp. 1430--1444, August 2007.
- J.-W. Fang, I.-J. Lin, Y.-W. Chang, and J.-H. Wang, "
A network-flow based RDL routing algorithm for flip chip design,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, No. 8, pp. pp. 1417--1429, August 2007.
- K. S.-M. Li, C.-L. Lee, Y.-W. Chang, C.-C. Su, and J. E Chen,
``Multilevel full-chip routing with testability and yield enhancement", in
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, No. 9, pp. 1625--1636, September 2007.
- P.-H. Yu, C.-L. Yang, and Y.-W. Chang,
``Temporal floorplanning using the three-dimensional transitive closure subgraph,"
ACM Trans. Design Automation of Electronic Systems, Vol. 12, No. 4, September 2007 (34 pages).
- B.-Y. Su and Y.-W. Chang,
``An optimal jumper insertion algorithm for antenna avoidance/fixing
,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, No. 10, pp. 1818--1929, October 2007.
- P.-H. Yu, C.-L. Yang, and Y.-W. Chang, "Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation," ACM Journal of Emerging Technologies in Computing Systems (JETC), Vol. 3, No. 3, November 2007 (32 pages).
- T.-C. Chen, Y.-W. Chang, and S.-C. Lin, "A new multilevel framework for large-scale
interconnect-driven floorplanning," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 2, pp. 286--294, February 2008.
- C.-W. Lin, S.-Y. Chen, C.-F. Li, Y.-W. Chang, and C.-L. Yang,
``Obstacle-avoiding rectilinear Steiner tree construction based on spanning graphs
," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 4, pp. 643--653, April 2008.
- T.-C. Chen, Y.-L. Chuang, and Y.-W. Chang,
``Effective wire models for X-architecture placement
," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 4, pp. 654--658, April 2008.
- H.-Y. Chen, M.-F. Chiang, Y.-W. Chang, L. Chen, and B. Han, "Full-chip routing considering double-via insertion," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 5, pp. 844--857, May 2008.
- Z.-W. Jiang and Y.-W. Chang, "An optimal network-flow-based simultaneous
diode and jumper insertion algorithm for antenna fixing,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 6, pp. 1055--1065, June 2008.
- T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang,
"NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 7, pp. 1228--1240, July 2008.
- C.-H. Liu, H.-Y. Liu, C.-W. Lin, S.-J. Chou, Y.-W. Chang, S.-Y. Kuo,
and S.-Y. Yuan, "An efficient graph-based algorithm for ESD current
path analysis," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 8, pp. 1363--1375, August 2008.
- T.-C. Chen, P.-H. Yuh, Y.-W. Chang, F.-J. Huang, and D. Liu, " MP-trees:
A packing-based macro placement algorithm for modern mixed-size designs,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 9, pp. 1621--1634, September 2008.
- C.-W. Lin, S.-L. Huang, K.-C. Hsu, M.-X. Li, and Y.-W. Chang, "Multi-layer obstacle-avoiding rectilinear Steiner tree construction based on spanning graphs," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 11, pp. 2007--2016, November 2008.
- P.-H. Yu, C.-L. Yang, and Y.-W. Chang,
"BioRoute: a network-flow based routing algorithm for the synthesis of
digital microfluidic biochips," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 11, pp. 1928--1941, November 2008.
- T.-C. Chen, M. Cho, D. Z. Pan, and Y.-W. Chang,
"Metal-density driven placement for CMP variation and routability,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 12, pp. 2145--2155, December 2008.
- J.-W. Fang, C.-H. Hsu, and Y.-W. Chang, "An integer linear programming based routing algorithm for flip-chip designs," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 28, No. 1, pp. 98--110, January 2009.
- H.-Y. Chen, S.-J. Chou, S.-L. Wang, and Y.-W. Chang,
"A novel wire-density-driven full-chip routing
system for CMP variation control," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD),
Vol. 28, No. 2, pp. 193--206, February 2009.
- W.-P. Lee, H.-Y. Liu, and Y.-W. Chang, "Voltage island partitioning and floorplanning under timing constraints,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD),
Vol. 28, No. 5, pp. 690--702, May 2009.
- P.-H. Lin, Y.-W. Chang, and S.-C. Lin,
"Analog placement based on symmetry-island and tree formulation,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD),
Vol. 28, No. 6, pp. 791--804, June 2009.
- P.-H. Yu, C.-L. Yang, and Y.-W. Chang,
"T-trees: A Tree-Based Representation for Temporal Floorplanning,"
ACM Trans. Design Automation of Electronic Systems, vol. 14, No. 4, August 2009.
- P.-H. Yu, S. Sapatnekar, C.-L. Yang, and Y.-W. Chang,
"A progressive-ILP based routing algorithm for cross-referencing biochips,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD),
Vol. 28, No. 9, pp. 1295--1306, Sept. 2009.
- H.-Y. Chen and Y.-W. Chang, "Routing for manufacturability and reliability,"
IEEE Circuits and Systems Magazine, pp. 20--31, September 2009 (invited feature article).
- T.-C. Chen, G.-W. Liao, and Y.-W. Chang, "Predictive formulae for OPC with applications to lithography-friendly routing," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 29, No. 1, pp. 40--50, January 2010.
- C.-H. Hsu, H.-Y. Chen, and Y.-W. Chang, "Multi-layer global routing with via and wire capacity considerations," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 29, No. 5, pp. 685--686, May 2010.
- K.-H. Ho, Y.-P. Chen, J.-W. Fang, and Y.-W. Chang, "ECO timing optimization using spare cells and technology remapping," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 29, No. 5, pp. 697--710, May 2010.
- J.-W. Fang and Y.-W. Chang, "Area-I/O flip-chip routing for chip-package co-design considering signal skews," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 29, No. 5, pp. 711--721, May 2010.
- C.-Y. Lin and Y.-W. Chang, "ILP-based pin-count aware design methodology for microfluidic biochips," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 29, No. 9, pp. 1315--1327, September 2010.
- C.-H. Hsu, Y.-W. Chang, and S. R. Nassif, "Simultaneous layout migration and decomposition for double patterning technology," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 30, No. 9, pp. 284--294, February 2011.
- M. P.-H. Lin, H. Zhang, M. D. F. Wong, and Y.-W. Chang, "Thermal-driven analog placement considering device matching," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 325--336, Vol. 30, No. 3, March 2011.
- C.-Y. Lin and Y.-W. Chang, "Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 817--828, Vol. 30, No. 6, June 2011.
- Y.-L. Chuang, S. Kim, Y. Shin, and Y.-W. Chang, "Pulsed-latch aware placement for timing-integrity optimization," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1649 - 1662, Vol. 30, No. 11, November 2011.
- Y.-L. Chuang, P.-W. Lee, and Y.-W. Chang, "Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1856--1869, Vol. 30, No. 12, December 2011.
- S.-Y. Fang, S.-Y. Chen, and Y.-W. Chang, "Native-conflict and switch-aware wire perturbation for double patterning technology," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 703-716, Vol. 31, No. 5, May 2012.
- C.-W. Lin, P.-W. Lee, Y.-W. Chang, C.-F. Shen, and W.-C. Tseng, "An efficient pre-assignment routing algorithm for flip-chip designs," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 878--889, Vol. 31, No. 6, June 2012.
- M.-K. Hsu and Y.-W. Chang, "Unified analytical global placement for large-scale mixed-size circuit designs," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1366-1378, Vol. 31, No. 9, September 2012.
- X.-W. Shih and Y.-W. Chang, "Fast timing-model independent buffered clock-tree synthesis," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1393-1404, Vol. 31, No. 9, September 2012.
- K.-H. Ho, J.-H. Jiang, and Y.-W. Chang, "TRECO: Dynamic technology remapping for timing engineering change orders," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1723--1733, Vol. 31, No. 11, November 2012.
- H.-Y. Chang, H.-R. Jiang, and Y.-W. Chang, "Timing ECO optimization via Bezier curve smoothing and fixability identification," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1857--1866, Vol. 31, No. 12, December 2012.
- S.-Y. Fang and Y.-W. Chang, "Graph-based subfield scheduling for electron-beam photomask fabrication," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 32, No. 2, pp. 189--201, February 2013.
- M.-K. Hsu, V. Balabanov, and Y.-W. Chang, "TSV-aware analytical placement for 3D IC designs based on a novel weighted-average wirelength model," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 32, No. 4, pp. 497--509, April 2013.
- Y.-W. Chang, "Technical perspective: circuit placement challenges," Communications of the ACM (CACM), Vol. 56, No. 6, p. 104, June 2013.
- Y.-K. Ho, H.-C. Lee, and Y.-W. Chang, "Escape routing for staggered-pin-array PCBs," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 32, No. 9, pp. 1347--1356, September 2013.
- H.-Y. Chang, I. H.-R. Jiang, Y.-W, Chang, "ECO optimization using metal-configurable gate-array spare cells," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 32, No. 11, pp. 1722--1733, November 2013.
- Y.-K. Ho, H.-C. Lee, P.-W. Lee, Y.-W. Chang, I.-J. Lin, and C. Shen, "Obstacle-avoiding free-assignment routing for flip-chip designs," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 33, No. 2, pp. 224--236, February 2014.
- S.-Y. Fang, Y.-W. Chang, and W.-Y. Chen, "A novel layout decomposition algorithm for triple patterning lithography," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 33, No. 3, pp. 397--408, March 2014.
- M.-K. Hsu, Y.-F. Chen, C.-C. Huang, S. Chou, T.-H. Lin, T.-C. Chen, and Y.-W. Chang, "NTUplace4h: A novel routability-driven placement algorithm for hierarchical mixed-size circuit designs," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 33, No. 12, p. 1914--1927, December 2014.
- H.-C. Ou, H.-C. Chang Chien, and Y.-W. Chang, "Non-uniform multilevel analog routing with matching constraints," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 33, No. 12, p. 1942--1954, December 2014.
- K.-H. Ho, H.-C. Ou, Y.-W. Chang, and H.-F. Tsao, "Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 34, No. 2, pp. 161--172, February 2015.
- I.-J. Liu, S.-Y. Fang, and Y.-W. Chang, "Stitch-aware routing for multiple e-beam lithography," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 34, No. 3, pp. 471--482, March 2015.
- H.-J. K. Chiang, C.-Y. Liu, J.-H. R. Jiang, and Y.-W. Chang, "Simultaneous EUV flare variation minimization and CMP control by coupling-aware dummification," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 35, No. 4, pp. 598--610, April 2016.
- H.-C. Ou, K.-H. Tseng, J.-Y. Liu, I-P. Wu, and Y.-W. Chang, "Layout-dependent-effects-aware analytical analog pPlacement," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 35, No. 8, pp. 1243--1254, August 2016.
- Y.-H. Su, Y.-C. Huang, L.-C. Tsai, Y.-W. Chang, and S. Banerjee, "Fast lithographic mask optimization considering process variation," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 35, No. 8, pp. 1345--1357, August 2016.
- I.-J. Liu, S.-Y. Fang, and Y.-W. Chang, "Overlay-aware detailed routing for self-aligned double patterning lithography using the cut process," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 35, No. 9, pp. 1519--1531, September 2016.
- Y.-H. Su and Y.-W. Chang, "Nanowire-aware routing considering high cut mask complexity," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 36, No. 6, pp. 964--977, June 2017.
- Y.-W. Chang, "An interview with Professor Chenming Hu, father of 3D transistors," IEEE Design & Test (D&T) , Vol. 34, Issue 5, pp. 90-96, October 2017
- Z.-W. Lin and Y.-W. Chang, "Cut redistribution with directed self-assembly templates for advanced 1-D gridded layouts,'' accepted and to appear in IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 36, No. 12, pp. 2066--2079, December 2017.
- C.-C. Huang, H.-Y. Lee, B.-Q. Lin, S.-W. Yang, C.-H. Chang, S.-T. Chen, Y.-W. Chang, T.-C. Chen, and I. Bustany,
"NTUplace4dr: a detailed-routing-driven placer for mixed-size circuit designs with technology and region constraints,"
in IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 36, No. 3, March 2018.
- Z.-W. Lin and Y.-W. Chang, "Provably good max-min-m-neighbor-TSP-based subfield scheduling for electron-beam photomask fabrication,'' accepted and to appear in IEEE Trans. Very Large Scale Integration Systems (TVLSI), 2018.
- Y.-H. Su and Y.-W. Chang, "DSA-compliant routing for two-dimensional patterns using block copolymer lithography,"
accepted and to appear in IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 36, 2018.
- Other Journal Papers:
- J.-M. Lin, H.-E. Yi, and Y.-W. Chang, "Module placement with
boundary constraints using B*-trees," in
IEE Proceedings--Circuits, Devices and Systems, Vol. 149, No. 4, pp. 251--256, August 2002. (EI/SCI)
- Y.-M. Lee, C.-P. Chen, Y.-W. Chang, and D.-F. Wong,
"Simultaneous buffer-sizing and wire-sizing for clock
trees based on Lagrangian relaxation," VLSI Design, Vol. 15, No. 3, pp. 587--594, November 2002 (invited paper). (EI/SCI)
- S.-W. Tu, W.-Z. Shen, Y.-W. Chang, T.-C. Chen, and J.-Y. Jou,
"Inductance modeling for on-chip interconnects,"
in International Journal of Analog Integrated Circuits and Signal Processing, Vol. 35, No. 1, pp. 65--78, April 2003 (invited paper). (EI/SCI)
- G.-M. Wu, M. Shyu, and Y.-W. Chang,
"Universal switch blocks for three-dimensional FPGA design,"
in IEE Proceedings---Circuits, Devices, and Systems, Vol. 151, No. 1, pp. 49-57, February 2004. (EI/SCI)
- G.-M. Wu, C.-T. M. Chao, and Y.-W. Chang,
"A clustering and probability based partitioning algorithm for
time-multiplexed FPGAs,"
in Integration: The VLSI Journal, Vol. 38, Issue 2, pp. 245-265, December 2004 (EI/SCI).
- T.-Y. Ho, Y.-W. Chang, and S.-J. Chen,
Multilevel Routing with Jumper Insertion for Antenna Avoidance, Integration: The VLSI Journal, Volume 39, Issue 4, pp. 420--432, July 2006 (EI/SCI).
- Y.-W. Chang, Z.-W. Jiang, and T.-C. Chen, "Essential issues in analytical placement algorithms," IPSJ Transactions on System LSI Design Methodology, Vol. 2, pp. 145--166, August 2009 (invited paper).
- Books and Book Chapters:
- M. Shyu, M.-H. Shieh, Y.-T. Chang, W.-H. Shiue, and Y.-W. Chang,
The Practical Xilinx Designer Lab Book
(translation in Chinese),
Chuan-Hwa Science &
Technology Book Co., 480 pages, Nov. 1998.
- Y.-W. Chang, D. F. Wong, and C. K. Wong,
``Programmable logic arrays'' in
Encyclopedia of Electrical and Electronics Engineering (John G. Webster, Editor),
John Wiley & Sons, Vol. 17, pp. 334-348, 1999 (invited article).
- Y.-W. Chang, T.-C. Chen, and H.-Y. Chen, "Physical Design for System-On-a-Chip" in
Essential Issues in SOC Design (Y.-L. Lin, Editor),
Springer, pp. 311-403, 2006 (invited article).
- T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang,
"NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs,"
(G.-J. Nam and J. Cong, Editors), 2007 (invited article).
- T.-Y. Ho, Y.-W. Chang, and S.-J. Chen,
Full-chip Nanometer Routing Techniques,
Springer, 2007.
- F. Y. Young, C.-K. Koh, and Y.-W. Chang,
"Buffer planning,"
in Physical Design Handbook (C. Alpert, S. Sapatnekar, and Dinesh D. Mehta, Editors),
CRC Press, 2008 (invited article).
- T.-C. Chen and Y.-W. Chang,
"Packing floorplan representation" in
Physical Design Handbook (C. Alpert, S. Sapatnekar, and Dinesh D. Mehta, Editors),
CRC Press, 2008 (invited article).
- L.-T. Wang, Y.-W. Chang, and K.-T. Cheng (editors),
Electronic Design Automation: Synthesis, Verification, and Testing,
Elsevier/Morgan Kaufmann, 2009 (934 pages).
- T.-C. Chen and Y.-W. Chang, "Floorplanning," in Electronic Design Automation: Synthesis, Verification, and Testing (L.T. Wang, Y.-W. Chang, and K.-T. Cheng, Editors), Elsevier/Morgan Kaufmann, 2009.
- H.-Y. Chen and Y.-W. Chang, "Global and Detailed Routing," in Electronic Design Automation: Synthesis, Verification, and Testing (L.T. Wang, Y.-W. Chang, and K.-T. Cheng, Editors), Elsevier/Morgan Kaufmann, 2009.
- C. E. Stroud, L.-T. Wang, and Y.-W. Chang, "Introduction," in Electronic Design Automation: Synthesis, Verification, and Testing (L.T. Wang, Y.-W. Chang, and K.-T. Cheng, Editors), Elsevier/Morgan Kaufmann, 2009.
- ACM/IEEE Conference Papers:
- K. Zhu, D. F. Wong, and Y.-W. Chang,
``Switch module design with application to two-dimensional segmentation design,''
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pp. 480--485, Santa Clara, CA, Nov. 1993.
- Y.-W. Chang, S. Thakur, K. Zhu, and D. F. Wong,
`` A new global routing algorithm for FPGAs,''
Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pp. 380--385, San Jose, CA, Nov. 1994.
- Y.-W. Chang, D. F. Wong, and C. K. Wong,
``FPGA global routing based on a new congestion metric,''
Proceedings of IEEE International Conference on Computer Design
(ICCD),
pp. 372--378, Austin, TX, Oct. 1995.
(Best Paper Award.)
- Y.-W. Chang, D. F. Wong, and C. K. Wong,
``Design and analysis of FPGA/FPIC switch modules,''
Proceedings of IEEE International Conference on Computer Design
(ICCD),
pp. 394--401, Austin, TX, Oct. 1995.
- Y.-W. Chang, D. F. Wong, and C. K. Wong,
``Universal switch-module design for symmetrical-array-based FPGAs,''
Proceedings of ACM International Symposium on Field Programmable
Gate Arrays (FPGA),
pp. 80--86, Monterey, CA, February 1996.
(Received the highest score.)
See an implementation report
for our universal switch modules
from Dept. of EECS, Univ. of California at Berkeley.
- Y.-W. Chang, D. F. Wong, K. Zhu, and C. K. Wong,
``On a new timing-driven routing tree problem,''
Proceedings of IEEE International Symposium on Circuits
and Systems (ISCAS),
pp. IV: 420--423, Atlanta, GA, May 1996.
- C.-P. Chen, Y.-W. Chang, and D. F. Wong,
``Fast performance-driven optimization for buffered clock
trees based on Lagrangian relaxation,''
Proceedings of 33rd ACM/IEEE Design Automation Conference (DAC),
pp. 405--408, Las Vegas, NV, June 1996.
- Y.-W. Chang, D. F. Wong, and C. K. Wong,
``A graph-theoretic sufficient condition for FPGA/FPIC switch-module routability,''
Proceedings of IEEE International Symposium on Circuits
and Systems (ISCAS),
vol. III, pp. 1572--1575, Hong Kong, June 1997.
- G.-M. Wu and Y.-W. Chang,
"Switch-matrix design and routing for FPDs,"
Proceedings of ACM International Symposium on Physical Design
(ISPD),
pp. 158-163, Monterey, CA, April 1998.
- G.-M. Wu and Y.-W. Chang,
"Maximally routable switch matrices for FPD design,"
Proceedings of IEEE International Symposium on Circuits
and Systems (ISCAS-98),
VI: 131--134, Monterey, CA, May 1998.
- K. Zhu, Y.-W. Chang, and D. F. Wong,
"Timing-driven routing for symmetrical-array-based FPGAs,"
Proceedings of IEEE International Conference on
Computer Design (ICCD-98),
pp. 628--633, Austin, TX, October 1998.
- Y.-W. Chang, J.-M. Lin, and D. F. Wong,
"Graph matching-based algorithms for FPGA segmentation design,"
Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-98),
pp. 34-39, Santa Clara, Nov. 1998.
- G.-M. Wu, M. Shyu, and Y.-W. Chang,
``Universal switch blocks for three-dimensional FPGA design,''
presented at 1999 ACM International Symposium on Field Programmable
Gate Arrays (FPGA-99) (poster),
Monterey, CA, February 1999.
This work was cited by the article
FPGA'99: Advanced processes unleash architectural ideas
in the EE Times weekly,
February 23, 1999.
- H.-R. Jiang, J.-Y. Jou, and Y.-W. Chang,
``Noise-constrained performance optimization by gate and wire sizing
based on Lagrangian relaxation,''
in Proc. of ACM/IEEE Design Automation Conference (DAC-99),
pp. 90-95, New Orleans, LA, June 1999.
- M. Shyu, Y.-D. Chang, G.-M. Wu, and Y.-W. Chang,
``Generic universal switch-block architectures and their interactions
with routing,''
in Proc. of IEEE International Conference on Computer Design (ICCD-99), pp. 311-314,
Austin, TX, Oct. 1999.
- C.-T. M. Chao, G.-M. Wu, H.-R. Jiang, and Y.-W. Chang,
``A clustering and probability based partitioning algorithm for
time-multiplexed FPGAs,"
in Proc. of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-99),
pp. 364-368, Santa Clara, CA, Nov. 1999.
- H.-R. Jiang, S.-R., Pan, Y.-W. Chang, and J.-Y. Jou,
``Reliable crosstalk-driven interconnect optimization,"
in Proc. of ACM International Symposium on Physical Design (ISPD-2000),
pp. 128-133, San Diego, CA, Apr. 2000.
- Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu,
``B*-trees: A new representation for non-slicing floorplans,"
in Proc. of ACM/IEEE Design Automation Conference (DAC-2000),
pp. 458-463,
LA, CA, June 2000.
(Best Paper Nominee)
- Y.-W. Chang and Y.-T. Chang,
``An architecture-driven metric for simultaneous placement and routing for FPGAs,"
in Proc. of ACM/IEEE Design Automation Conference (DAC-2000),
pp. 567-572, LA, CA, June 2000.
- G.-M. Wu, Y.-C. Chang, and Y.-W. Chang,
``Rectilinear block placement using B*-trees,"
in Proc. of IEEE International Conference on Computer Design (ICCD-00),
pp. 351-356, Austin, TX, Oct. 2000.
- S.-R. Pan and Y.-W. Chang,
``Crosstalk-constrained Performance Optimization by Using Wire Sizing
and Perturbation,"
in Proc. of IEEE International Conference on Computer Design (ICCD-00), pp. 581-584,
Austin, TX, Oct. 2000.
- J.-M. Lin and Y.-W. Chang,
``TCG: A transitive closure graph based representation for non-slicing floorplans,"
in Proc. of ACM/IEEE Design Automation Conference (DAC-2001),
pp. 764--769, Las Vegas, NV, June 2001.
- T.-C. Chen, S.-R. Pan, and Y.-W. Chang,
``Performance optimization by wire and buffer sizing under the transmission line model,"
in Proc. of IEEE International Conference on Computer Design (ICCD-01),
pp. 192--197, Austin, TX, Nov. 2001.
- G.-M. Wu, J.-M. Lin, M. C.-T. Chao, and Y.-W. Chang,
``Generic ILP-based approaches for dynamically reconfigurable FPGA partitioning
,"
in Proc. of IEEE International Conference on Computer Design (ICCD-01),
pp. 335--340, Austin, TX, Nov. 2001.
(Best Paper Nominee)
- G.-M. Wu and Y.-W. Chang,
``An Algorithm for Dynamically Reconfigurable FPGA Placement,"
in Proc. of IEEE International Conference on Computer Design (ICCD-01),
pp. 501--504, Austin, TX, Nov. 2001.
- C.-Y. Chang, H.-R. Jiang, and Y.-W. Chang,
"Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning,"
in 2002 IEEE International Symposium on Quality of Electronic Design (ISQED 2002),
pp. 523--528, San Jose, CA, March 2002.
- J.-M. Lin, H.-L. Lin, and Y.-W. Chang,
``Arbitrary Convex and Concave Rectilinear Module Packing Using TCG,"
in Proc. of ACM/IEEE Design Automation and Test in Europe (DATE-2002),
pp. 69--75, Paris, France, March 2002.
- S.-W. Tu, W.-Z. Shen, Y.-W. Chang, and T.-C. Chen,
``Inductance modeling for on-chip interconnects,"
in Proceedings of the IEEE Symposium on Circuits and Systems (ISCAS-2002),
vol. 3, pp. 787--790, Pheonix, AZ, May 2002.
- J.-M. Lin and Y.-W. Chang,
``TCG-S: Orthogonal Coupling of P*-admissible Representations for General Floorplans,"
in Proc. of ACM/IEEE Design Automation Conference (DAC-2002),
pp. 842--847, New Orleans, June 2002.
- S.-P. Lin and Y.-W. Chang,
"A novel framework for multilevel routing considering routability and performance,"
in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2002),
pp. 44--50, San Jose, Nov. 2002. (Best Paper Nominee)
- S.-M. Li, Y.-H. Cherng, and Y.-W. Chang,
``Noise-aware buffer planning for interconnect-driven floorplanning,"
in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2003),
pp. 423--426, Kitakyushu, Japan, January. 2003.
- H.-R. Jiang, Y.-W. Chang, J.-Y. Jou, and K.-Y. Chao,
``Simultaneous Floorplanning and Buffer Block Planning,"
in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2003),
pp. 431--434, Kitakyushu, Japan, January. 2003.
- J.-M. Lin, S.-R. Pan, and Y.-W. Chang,
``Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing,"
in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2003),
pp. 851--854, Kitakyushu, Japan, January. 2003.
- H.-C. Lee, Y.-W. Chang, J.-M. Hsu, and H. Yang,
``Multilevel floorplanning/placement for large-scale modules using
B*-trees,"
in Proc. of ACM/IEEE Design Automation Conference (DAC-2003),
pp. 812--817, Anaheim, CA, June 2003.
- T.-Y. Ho, Y.-W. Chang, S.-J. Chen, and D. T. Lee,
"A fast crosstalk- and performance-driven multilevel routing system,"
in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2003),
pp. 382--387, San Jose, Nov. 2003.
- Y.-H. Cheng and Y.-W. Chang,
``Integrating buffer planning with floorplanning for simultaneous
multi-objective Optimization,"
in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2004),
pp. 624--627, Yokohama, Japan, January 2004.
- S.-W. Tu, J.-Y. Jou, and Y.-W. Chang, "Layout techniques for
for on-chip interconnect inductance reduction,"
in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2004),
pp. 269-273, Yokohama, Japan, January 2004.
- P.-H. Yu, C.-L.Yang, Y.-W. Chang, and H.-L. Chen,
"Temporal floorplanning using 3D-subTCG,"
in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2004),
pp. 725--730, Yokohama, Japan, January 2004. (Best Paper Nominee)
- T.-Y. Ho, Y.-W. Chang, and S.-J. Chen,
"Multilevel routing with antenna avoidance,"
in Proceedings of ACM International Symposium on Physical Design (ISPD-2004),
pp. 34--40, Phoenix, Arizona, April 2004.
- S.-W. Tu, J.-Y. Jou, and Y.-W. Chang, "RLC effects on worst-case switching patterns for on-chip buses,"
in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS-2004),
Vol. 2, pp. 945--948, Vancouver, Canada, May 2004.
- S.-W. Wu and Y.-W. Chang,
``Efficient power/ground network analysis for power integrity driven design methodology,"
in Proc. of ACM/IEEE Design Automation Conference (DAC-2004),
pp. 177--180, San Diego, CA, June 2004.
- T.-Y. Ho, Y.-W. Chang, and S.-J. Chen,
"Multilevel routing with jumper insertion for antenna avoidance,"
in Proceedings of IEEE International SOC Conference (SOC-2004),
pp. 63--66, Santa Clara, California, September 2004.
- M.-C. Wu and Y.-W. Chang, "Placement with Alignment and Performance Constraints Using the B*-tree representation,"
in Proceedings of IEEE International Conference on Computer Design (ICCD-2004),
pp. 568--571, San Jose, CA, September 2004.
- P.-H. Yu, C.-L.Yang and Y.-W. Chang,
"Temporal floorplanning using the T-tree formulation,"
in Proceedings of IEEE/ACM International Conference on computer-Aided Design (ICCAD-2004),
pp. 300--305, San Jose, CA, November 2004.
- J.-M. Hsu and Y.-W. Chang, "A reusable methodology for non-slicing floorplanning,"
in Proceedings of IEEE Asia and Pacific Conference on Circuits and Systems (APCCAS-2004),
Tainan, Taiwan, December 2004.
- T.-C. Chen and Y.-W. Chang,
"Multilevel gridless routing considering optical proximity effects,"
in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2005),
pp. 1160--1163, Shanghai, China, January 2005.
- J.-Y. Wuu, T.-C. Chen, and Y.-W. Chang,
"SoC test scheduling using the B*-tree based flooprlanning technique,"
in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2005),
pp. 1188--1191, Shanghai, China, January 2005.
- G.-M. Wu, J.-M. Lin, Y.-W. Chang, and R.-H. Chuang,
"Placement with symmetry constraints for analog layout design,"
in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2005),
pp. 1135--1138, Shanghai, China, January 2005.
- T.-C. Chen and Y.-W. Chang,
"Modern floorplanning based on fast simulated annealing,"
in Proceedings of ACM International Symposium on Physical Design (ISPD-2005),
pp. 104--112, San Francisco, CA, April 2005.
- T.-C. Chen, T.-C. Hsu, Z.-W. Jiang, and Y.-W. Chang,
"NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs,"
in Proceedings of ACM International Symposium on Physical Design (ISPD-2005), pp. 236--238,
San Francisco, CA, April 2005.
- S.-M Lee, C.-W. Lee, Y.-W. Chang, C.-C. Su, and J.-Y. Chen,
"Multilevel full-chip routing with testability and yield enhancement,"
in Proceedings of ACM International Workshop on System Level Interconnect Prediction (SLIP-2005),
pp. 29--36, San Francisco, CA, April 2005.
- S.-L. Wang and Y.-W. Chang,
"Delay modelling for buffered RLC/RLY trees,"
in Proceedings of The 1st IEEE-TSA VLSI Design Automation and Test Conference (VLSI-DAT-2005), Hsinchu, Taiwan, April 2005.
- S.-W. Tu, J.-Y. Jou, and Y.-W. Chang,
"RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction,"
in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS-2005),
pp. 4134--4137, Kobe, Japan, May 2005.
- B.-Y. Su and Y.-W. Chang,
``An optimal jumper insertion algorithm for antenna effect avoidance/fixing
,"
in Proc. of ACM/IEEE Design Automation Conference (DAC-2005),
pp. 325--328, Anaheim, CA, June 2005.
- T.-Y. Ho, C.-F. Chang, Y.-W. Chang, and S.-J. Chen,
``Multilevel full-chip routing for the X-based
architecture,"
in Proc. of ACM/IEEE Design Automation Conference (DAC-2005),
pp. 597--602, Anaheim, CA, June 2005. (Best Paper Nominee)
- Y.-W. Wu, P.-H. Yuh, C.-L. Yang, and Y.-W. Chang, "Joint
exploration of architectural and physical
design spaces with thermal consideration," in Proceedings of IEEE/ACM International Symposium
on Low Power Electronic Design (ISLPED-05), pp. 123--126, August 2005.
- C.-S. Shih, C.-L. Yang, M.-K. Ku, T.-W. Kuo, S.-Y. Chien, Y.-W. Chang, L.-G. Chen,
"Reconfigurable Platform for Content Science Research,"
in Proceedings of the 11th IEEE International Conference on RTCSA,
pp. 481--488, Hong Kong, China, 2005.
- T.-C. Chen, Y.-W. Chang, and C.-C. Lin, "IMF:
Interconnect-driven multilevel floorplanning for large-scale building-module designs,"
in Proceedings of IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-2005),
pp. 159--164, San Jose, Nov. 2005.
- J.-W. Fang, I.-J. Lin, P.-H. Yuh, Y.-W. Chang, and J.-H. Wang, "A routing algorithm for flip chip
design,"
in Proceedings of IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-2005),
pp. 753--758, San Jose, Nov. 2005.
- C.-Y. Peng, W.-C. Chao, Y.-W. Chang, and J.-H. Wang,
"Simultaneous block and I/O buffer floorplanning
for flip-chip design," in Proceedings of ACM/IEEE Asia South Pacific Design Automation
Conference (ASP-DAC-2006),
pp. 213--218, Yokohama, Japan, January 2006.
- K. S.-M. Li, Y.-W. Chang, C.-C. Su, C.-L. Lee, and J. E. Chen,
"P1500 based interconnect diagnosis for delay and
crosstalk faults"
in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference
(ASP-DAC-2006),
pp. 366--371, Yokohama, Japan, January 2006.
- T.-C. Chen, Y.-W. Chang, and S.-C. Lin,
"A novel framework for multilevel full-chip gridless
routing,"
in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference
(ASP-DAC-2006),
pp. 636--641, Yokohama, Japan, January 2006.
- C.-W. Liu and Y.-W. Chang, "Floorplan and power/ground network
co-synthesis for fast design
convergence," to appear in Proceedings of ACM International Symposium on Physical Design
(ISPD-2006), San Jose, CA, April 2006.
- B.-Y. Su, Y.-W. Chang, and J. Hu,
``An optimal jumper insertion algorithm for antenna effect
avoidance/fixing on general routing trees
with obstacles," to appear in Proceedings of ACM International Symposium on Physical Design
(ISPD-2006), San Jose, CA, April 2006.
- T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang,
"NTUplace2: a hybrid placer using partitioning and analytical techniques,"
in Proceedings of ACM/IEEE International Symposium on Physical Design (ISPD-2006), pp. 215--217,
San Jose, CA, April 2006. (Won the 3rd place in the placement contest; #1 in wirelength cost, #2 in overall quality [less than 1% away from the #1], #3 in overall combined cost, quality + CPU time [less than 2% away from the #1])
- Y.-W. Lin and Y.-W. Chang, "Thermal-driven interconnect optimization by gate and wire sizing,"
in Proceedings of The 2nd IEEE-TSA VLSI Design Automation and Test Conference
(VLSI-DAT-2006), pp. 151--154, Hsinchu, Taiwan, April 2006.
- C.-Y. Lai, S.-K. Jeng, Y.-W. Chang, and C.-C. Tsai,
"Surface integral inductance extraction for general interconnect structures,"
in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS-2006),
Kos, Greece, May 2006.
- H.-Y. Chen, M.-F. Chiang, Y.-W. Chang, L. Chen, and B. Han, "Novel full-chip gridless routing considering double-via insertion," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2006), pp. 755--760,
San Francisco, CA, July 2006.
- P-H. Yuh, C.-L. Yang, and Y.-W. Chang, "Placement of digital microfluidic biochips using the T-tree formulation," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2006),
pp. 931--934, San Francisco, CA, July 2006.
- T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, "A high quality analytical placer considering preplaced blocks and density constraint," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-2006), pp. 187--192, San Jose, Nov. 2006. (Received the highest score in the partitioning/floorplanning/placement track)
- W.-P. Lee, H.-Y. Liu, and Y.-W. Chang, "Voltage island aware floorplanning for power and timing optimization," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-2006), pp. 389--394, San Jose, Nov. 2006.
- H.-Y. Liu, C.-W. Lin, S.-J. Chou, W.-T. Tu, Y.-W. Chang, and S.-Y. Kuo, "Current path analysis for electrostatic discharge protection," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-2006), pp. 510--515, San Jose, Nov. 2006.
- Z.-W. Jiang and Y.-W. Chang, "An optimal simultaneous diode/jumper insertion algorithm for antenna fixing," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-2006), pp. 669--674, San Jose, Nov. 2006.
- C.-W. Lin, M.-C. Tsai, K.-Y. Lee, T.-C. Chen, T.-C. Wang,
and Y.-W. Chang,
"Recent research and emerging challenges in physical design for manufacturability/reliability,"
in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference
(ASP-DAC-2007),
pp. 238--243, Yokohama, Japan, January 2007. (invited paper)
- I.-J. Lin, T.-Y. Lin, and Y.-W. Chang,
``Statistical circuit optimization considering device and interconnect process variations," to appear in Proceedings of ACM International Workshop on System Level Interconnect Prediction
(SLIP-2007), Austin, TX, March 2007.
- T.-C. Chen, Y.-L. Chuang, and Y.-W. Chang, "X-architecture placement based on effective wire models," in Proceedings of ACM International Symposium on Physical Design
(ISPD-2007), pp. 87--94, Austin, TX, March 2007. (Best Paper Nominee; received the highest score)
- C.-W. Lin, S.-Y. Chen, C.-F. Li, Y.-W. Chang, and C.-L. Yang,
``Efficient obstacle-avoiding rectilinear Steiner tree construction," in Proceedings of ACM International Symposium on Physical Design
(ISPD-2007), pp. 127--134, Austin, TX, March 2007. (Best Paper Nominee)
- Z.-W. Jiang, H.-C. Chen, T.-C. Chen, and Y.-W. Chang,
"Challenges and solutions in modern VLSI placement,"
in Proceedings of The 3rd IEEE-TSA VLSI Design Automation and Test Conference
(VLSI-DAT-2007), pp. 111--115, Hsinchu, Taiwan, April 2007. (invited paper)
- J.-W. Fang, C.-H. Hsu, and Y.-W. Chang,
"An integer linear programming algorithm for flip-chip routing,"
in Proceedings of ACM/IEEE Design Automation Conference (DAC-2007),
San Diego, CA, June 2007. (Best Paper Nominee; received the highest score in the beyond-die track)
- T.-C. Chen, P.-H. Yuh, Y.-W. Chang, F.-J. Liu, and D. Liu,
"MP-trees: a packing-based macro placement algorithm for mixed-size designs,"
in Proceedings of ACM/IEEE Design Automation Conference (DAC-2007),
San Diego, CA, June 2007. (received the 2nd highest score out of 52 papers in the physical design and manufacturability track)
- H.-Y. Liu, W.-P. Lee, and Y.-W. Chang,
"A provably good approximation algorithm for power optimization using
multiple supply voltages,"
in Proceedings of ACM/IEEE Design Automation Conference (DAC-2007),
San Diego, CA, June 2007.
- C.-F. Li, P.-H. Yuh, C.-L. Yang, and Y.-W. Chang,
"Post-placement leakage optimization for partially dynamically reconfigurable FPGAs," in Proceedings of IEEE/ACM International Symposium
on Low Power Electronic Design (ISLPED-07), August 2007.
- W.-P. Lee, H.-Y. Liu, and Y.-W. Chang, "An ILP algorithm for post-floorplanning voltage-island generation,
in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007.
- Y.-P. Chen, J.-W. Fang, and Y.-W. Chang, "ECO timing optimization using spare cells,
in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007.
- I.-J. Lin and Y.-W. Chang, "An efficient algorithm for statistical
circuit optimization using Lagrangian relaxation,
in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007.
- C.-W. Lin. S.-L. Huang, K.-C. Hsu, M.-X. Lee, and Y.-W. Chang, "Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction,
in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007.
- H.-Y. Chen, S.-J. Chou, S.-L. Wang, and Y.-W. Chang, "Novel wire density driven full-chip routing for CMP variation control,
in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007. (Best Paper Nominee)
- P.-H. Yu, C.-L. Yang, and Y.-W. Chang, "BioRoute: A network flow based routing algorithm for digital microfluidic biochips,
in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007.
- T.-C. Chen, M. Cho, D. Z. Pan and Y.-W. Chang, "Metal-density driven placement for CMP variation and routability," in Proceedings of ACM International Symposium on Physical Design
(ISPD-2008), Portland, Oregon, April 2008.
- W.-P. Lee, H.-Y. Liu, K.-H. Ho, and Y.-W. Chang, "Sensitivity-based
multiple-Vt cell swapping for leakage power reduction under timing
requirements,"
in Proceedings of The 4th IEEE-TSA VLSI Design Automation and Test
Conference (VLSI-DAT-2008), Hsinchu, Taiwan, April 2008.
- T.-C. Chen, G.-W. Liao, and Y.-W. Chang,
"Predictive formulae for OPC with applications to lithography-friendly routing,"
in Proceedings of ACM/IEEE Design Automation Conference (DAC-2008),
Anaheim, CA, June 2008. (Best Paper Nominee; received the highest score in the Physical Design & Manufacturability track)
- Z.-W. Jiang, B.-Y. Su, and Y.-W. Chang,
"Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs,"
in Proceedings of ACM/IEEE Design Automation Conference (DAC-2008),
Anaheim, CA, June 2008.
- P.-H. Yuh, S. Sapatnekar, C.-L. Yang, and Y.-W. Chang,
"A progressive-ILP based routing algorithm for cross-referencing biochips,"
in Proceedings of ACM/IEEE Design Automation Conference (DAC-2008),
Anaheim, CA, June 2008.
- J.-W. Fang and Y.-W. Chang, "Area-I/O flip-chip routing for chip-package co-design,"
in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2008), San Jose, Nov. 2008.
- J.-W. Fang, K.-H. Ho, and Y.-W. Chang, "Placement and routing for chip-package-board co-design considering differential pairs,"
in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2008), San Jose, Nov. 2008.
- C.-H. Hsu, H.-Y. Chen, and Y.-W. Chang, "Multi-layer global routing considering via and wire capacities,"
in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2008), San Jose, Nov. 2008.
- H.-C. Chen, Y.-L. Chuang, Y.-W. Chang, and Y.-C. Chang, "Constraint graph-based macro placement for mixed-size circuit designs,"
in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2008), San Jose, Nov. 2008.
- C.-H. Hsu, H.-Y. Chen, and Y.-W. Chang, "
High-performance global routing with fast overflow reduction," in Proceedings
of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2009),
Yokohama, Japan, January 2009.
- H. Graeb, F. Balasa, R. Castro-Lopez, Y.-W. Chang, F. Fernandez, P.-H. Lin, M. Strasser, "Analog Layout Synthesis - Recent Approaches," in Proceedings of ACM/IEEE Design Automation and Test in Europe (DATE-2009), Niece, France, March 2009.
- W.-P. Lee, D. Marculescu, and Y.-W. Chang,
"Post-Floorplanning Power/Ground Ring Synthesis for Multiple-Supply-Voltage Designs," in Proceedings of ACM International Symposium on Physical Design (ISPD-2009), San Diego, CA, April 2009.
- C.-Y. Lin and Y.-W. Chang, "ILP-based pin-count aware design methodology for microfluidic biochips," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2009), San Francisco, CA, July 2009.
- P.-H. Lin, H. Zhang, D. F. Wong, and Y.-W. Chang, "Thermal-driven analog placement considering device matching," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2009), San Francisco, CA, July 2009.
- Z.-W. Jiang, M-K. Hsu, Y.-W. Chang, and K.-Y. Chao, "Spare-cell-aware multilevel analytical placement," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2009), San Francisco, CA, July 2009.
- J.-W. Fang, D. F. Wong, and Y.-W. Chang, "Flip-chip routing with unified area-I/O pad assignments for package-board co-design," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2009), San Francisco, CA, July 2009.
- Y.-L. Chuang, P.-W. Lee, and Y.-W. Chang, "Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2009), San Jose, Nov. 2009. (Best Paper Nominee)
- P.-W. Lee, C.-W. Lin, Y.-W. Chang, "An efficient pre-assignment routing algorithm for flip-chip designs," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2009), San Jose, Nov. 2009.
- C.-H. Hsu, Y.-W. Chang, S. R. Nassif, "Simultaneous layout migration and decomposition for double patterning technology," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2009), San Jose, Nov. 2009.
- T.-F. Chien, W.-C. Chao, Chien-Mo Li, K.-Y. Liao, Y.-W. Chang, M.-T. Chang, M.-H. Tsai, and C.-M. Tseng, " BIST design optimization for large-scale embedded memory cores," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2009), San Jose, Nov. 2009.
- X.-W. Shih, C.-C. Cheng, Y.-K. Ho, and Y.-W. Chang, "Blockage-avoiding buffered clock-tree synthesis for clock
latency-range and skew minimization," in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2010), Taipei, Taiwan, January 2010.
- K.-H. Ho, J.-H. Jiang, Y.-W. Chang, "TRECO: Dynamic technology remapping for timing engineering change orders," in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2010), Taipei, Taiwan, January 2010.
- P. Falkenstern, Y. Xie, Y. Wang, and Y.-W. Chang, " Three-dimensional integrated circuit (3D IC) floorplan and power/ground network co-synthesis," in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2010), Taipei, Taiwan, January 2010.
- H.-Y. Chen, S.-J. Chou, and Y.-W. Chang, "Density gradient minimization with coupling-constrained dummy fill for CMP control ," in Proceedings of ACM International Symposium on Physical Design (ISPD-2010), San Francisco, CA, March 2010.
- X.-W. Shih and Y.-W. Chang, "Fast timing-model independent clock-tree synthesis," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2010), Anaheim, CA, June 2010.
- C.-Y. Lin and Y.-W. Chang, "Cross contamination aware design methodology for pin-constrained digital microfludic biochips," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2010), Anaheim, CA, June 2010.
- Y.-L. Chuang, S. Kim, Y. Shin, and Y.-W. Chang, "Pulsed-latch-aware placement for timing-integrity optimization," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2010), Anaheim, CA, June 2010.
- S.-L. Huang, C.-W. Lin, and Y.-W. Chang, "Provably good OPC modeling and its applications to interconnect optimization," in Proceedings of IEEE International Conference on Computer Design (ICCD-2010), Amsterdam, Netherland, October 2010. (Best Paper Award)
- H.-C. Lee, Y.-W. Chang, and P.-W. Lee, "Recent research development in flip-chip routing," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2010), San Jose, November 2010. (invited embedded tutorial paper)
- S.-Y. Chen and Y.-W. Chang, "Native-conflict-aware wire perturbation for double patterning technology," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2010), San Jose, November 2010.(Best Paper Nominee)
- M.-K. Hsu and Y.-W. Chang, "Unified analytical global placement for large-scale mixed-size circuit designs," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2010), San Jose, November 2010.
- S.-Y. Fang, T.-F. Chien, and Y.-W. Chang, "Redundant-wires-aware ECO timing and mask-cost optimization," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2010), San Jose, November 2010.
- C.-H. Hsu, Y.-W. Chan, and R. S. Nassif, "Template-mask design methodology for double patterning technology," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2010), San Jose, November 2010.
- X.-W. Shih, H.-C. Lee, K.-H. Ho, and Y.-W. Chang, "High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2010), San Jose, November 2010.
- Y.-L. Chuang, G.-J. Nam, C. J. Alpert, Y.-W. Chang, J. Roy, and N. Viswanathan, "Design-hierarchy aware mixed-size placement for routability optimization," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2010), San Jose, November 2010.
- M.-K. Hsu, Y.-W. Chang, and V. Balabanov, "TSV-aware analytical placement for 3D IC designs," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2011), San Diego, CA, June 2011. (Best Paper Nominee)
- H.-Y. Chang, H.-R. I. Jiang, and Y.-W. Chang, "Simultaneous functional and timing ECO," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2011), San Diego, CA, June 2011.
- P.-Y. Chou, H.-C. Ou, Y.-W. Chang, "Heterogeneous B*-trees for analog placement with symmetry and regularity considerations," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2011), San Jose, November 2011.
- H.-Y. Chang, I. H.-R. Jiang, and Y.-W. Chang, "Timing ECO optimization via Bezier curve smoothing and fixability identification," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2011), San Jose, November 2011.
- Y.-K. Ho, H.-C. Lee, and Y.-W. Chang, "Escape routing for staggered-pin-array PCBs," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2011), San Jose, November 2011.
- H.-F. Tsao, P.-Y. Chou, S.-L. Huang, Y.-W. Chang, M. P.-H. Lin, D.-P. Chen, and D. Liu, "A corner stitching compliant B*-tree representation and its applications to analog placement," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2011), San Jose, November 2011.
- Y.-L. Chuang, H.-T. Lin, T.-Y. Ho, Y.-W. Chang, and D. Marculescu, "PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2011), San Jose, November 2011.
- M.-K. Hsu, S. Chou, T.-H. Lin, and Y.-W. Chang, "A novel routability-driven analytical placement algorithm for large-scale mixed-size circuit designs," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2011), San Jose, November 2011.
- D.-C. Juan, Y.-L. Chuang, D. Marculescu, and Y.-W. Chang, "Statistical Thermal Modeling and Optimization Considering Leakage Power Variations," to appear in Proceedings of IEEE/ACM European Design Automation and Test Conference (DATE-2012), Dresden, Germany, March 2012.
- S.-Y. Fang and Y.-W. Chang, "Graph-based subfield scheduling for electron-beam photomask fabrication," in Proceedings of ACM International symposium on Physical Design (ISPD-2012), Napa, CA, March 2012. (Best paper nominee; 5 nominees)
- S.-Y. Fang and Y.-W. Chang, "Simultaneous flare level and flare variation minimization with dummification in EUVL," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2012), San Francisco, CA, June 2012.
- H.-C. Lee and Y.-W. Chang, "A chip-package-board co-design methodology," n Proceedings of ACM/IEEE Design Automation Conference (DAC-2012), San Francisco, CA, June 2012.
- S. Chou, M.-K. Hsu, and Y.-W. Chang, "Structure-aware placement for datapath intensive circuit designs," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2012), San Francisco, CA, June 2012.
- S.-Y. Fang and Y.-W. Chang, "A novel layout decomposition algorithm for triple patterning lithography," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2012), San Francisco, CA, June 2012.
- H.-C. Oh, S.-C. Chang-Chien, and Y.-W. Chang, "Non-uniform multilevel analog routing with matching constraints," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2012), San Francisco, CA, June 2012.
- H.-Y. Chang, H.-R. Jiang, and Y.-W. Chang, "Timing ECO optimization using metal-configurable gate-array spare cells," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2012), San Francisco, CA, June 2012.
- P.-W. Lee, H.-C. Lee, Y.-K. Ho, Y.-W. Chang, I.-J. Lin, and C. Shen, "Obstacle-avoiding free-assignment routing for flip-chip designs," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2012), San Francisco, CA, June 2012.
- Y.-K. Ho, X.-W. Shih, Y.-W. Chang, and C.-K. Cheng, " Layer minimization in escape routing for staggered-pin-array PCBs," in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2013), Yokohama, Japan, January 2013.
- X.-W. Shih, T.-H. Hsu, H.-C. Lee, Y.-W. Chang, and K.-Y. Chao, " Symmetrical buffered clock-tree synthesis with supply-voltage alignment," in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2013), Yokohama, Japan, January 2013.
- S.-Y. Fang, C.-W. Lin, G.-W. Liao, and Y.-W. Chang, "Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling," to appear in Proceedings of ACM International symposium on Physical Design (ISPD-2013), Stateline, NV, March 2013.(Best Paper Nominee)
- S.-Y. Fang, I.-J. Liu, and Y.-W. Chang, "Stitch-aware routing framework for multiple e-beam lithography," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2013), Austin, TX, June 2013.
- H.-C. Chang-Chien, H.-C. Ou, T.-C. Chen, and Y.-W. Chang, "Double patterning lithography-aware analog placement," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2013), Austin, TX, June 2013.
- H.-C. Ou, K.-H. Ho, Y.-W. Chang, and H.-F. Tsao, "Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2013), Austin, TX, June 2013.
- T.-H. Lin, P. Banerjee, and Y.-W. Chang, "An efficient and effective analytical placer for FPGAs," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2013), Austin, TX, June 2013.
- Y.-K. Ho and Y.-W. Chang, "Multiple chip planning for chip-interposer codesign," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2013), Austin, TX, June 2013.
- H.-C. Oh, S.-C. Chang-Chien, and Y.-W. Chang, "Simultaneous analog placement and pouting with current flow and current density considerations," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2013), Austin, TX, June 2013.
- M.-K. Hsu, Y.-F. Chen, C.-C. Huang, T.-C. Chen, and Y.-W. Chang, "Routability-driven placement for hierarchical mixed-size circuit designs," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2013), Austin, TX, June 2013.
- I.-J. Liu, S.-Y. Fang, and Y.-W. Chang, "Overlay-aware detailed routing for self-aligned double patterning lithography using the cut process," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2014), San Francisco, CA, June 2014.
- K.-H. Ho and Y.-W. Chang, "A new asynchronous pipeline template for power and performance optimization," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2014), San Francisco, CA, June 2014.
- H.-Y. Chang, I. H.-R. Jiang, and Y.-W. Chang, "Functional ECO using metal-configurable gate-array spare cells," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2014), San Francisco, CA, June 2014.
- Y.-F. Chen, C.-C. Huang, C.-H. Chiou, and Y.-W. Chang, "Routability-driven blockage-aware macro placement," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2014), San Francisco, CA, June 2014.
- C.-Y. Liu, H.-J. Jiang, Y.-W. Chang, and J.-H. Jiang, "Simultaneous EUV flare variation minimization and CMP control with coupling-aware dummification," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2014), San Francisco, CA, June 2014.
- C.-W. Lin, T.-H. Lin, X.-W. Lin, and Y.-W. Chang, "Buffered clock tree synthesis considering self-heating effects," in Proceedings of ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED-2014), La Jolla, CA, August 2014.
- C.-Y. Liu and Y.-W. Chang, "Simultaneous EUV flare- and CMP-aware placement," in Proceedings of IEEE International Conference on Computer Design (ICCD-2014), Seoul, Korea, October 2014.
- Y.-H. Su, Y.-C. Huang, L.-C. Tsai, Y.-W. Chang, and S. Banerjee, "Fast Lithographic Mask Optimization Considering Process Variation," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2014), San Jose, November 2014.
- Y.-C. Chen, S.-Y. Chen, and Y.-W. Chang, "Efficient and Effective Packing and Analytical Placement for Large-Scale Heterogeneous FPGAs," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2014), San Jose, November 2014.
- S.-Y. Fang, Y.-S. Tai, and Y.-W. Chang, "Layout Decomposition for Spacer-is-Metal (SIM) Self-Aligned Double Patterning," in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2015), Tokyo, Japan, January 2015.
- P.-Y. Hsu and Y.-W. Chang, "Non-stitch triple patterning-aware routing based on conflict graph pre-coloring," in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2015), Tokyo, Japan, January 2015.
- C.-C. Huang, C.-H. Chiou, K.-H. Tseng, and Y.-W. Chang, "Detailed-routing-driven analytical standard-cell placement," in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2015), Tokyo, Japan, January 2015.
- Y.-W. Chang, R.-G. Liu, and S.-Y. Fang, "EUV and e-beam manufacturability: challenges and solutions," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2015), San Francisco, CA, June 2015. (Invited Paper)
- S.-Y. Chen and Y.-W. Chang, "Routing-architecture-aware analytical placement for heterogeneous FPGAs," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2015), San Francisco, CA, June 2015.
- Y.-H. Su and Y.-W. Chang, "Nanowire-aware routing considering high cut-mask complexity," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2015), San Francisco, CA, June 2015.
- H.-C. Ou, K.-H. Tseng, J.-Y. Liu, I-. Wu, and Y.-W. Chang, "Layout-dependent-effects-aware analytical analog placement," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2015), San Francisco, CA, June 2015.
- H.-C. Ou, K.-H. Tseng, and Y.-W. Chang, "Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2015), San Francisco, CA, June 2015.
- C.-C. Huang, H.-Y. Lee, B.-Q. Lin, S.-W. Yang, C.-H. Chang, S.-T. Chen, and Y.-W. Chang, "Detailed-routability-driven analytical placement for mixed-size designs with technology and region constraints," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2015), Austin, TX, November 2015.
- Z.-W. Lin, S.-Y. Fang, Y.-W. Chang, W.-C. Rao, and C.-H. Kuan, "Provably Good Max-Min-m-neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2015), Austin, TX, November 2015.
- Z.-W. Lin and Y.-W. Chang, "Cut redistribution with directed self-assembly templates for advanced 1-D gridded layouts," in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2016), Macau, January 2016.
- C.-H. Chiou, C.-H. Chang, S.-T. Chen, and Y.-W. Chang, "Circular-Contour-Based Obstacle-Aware Macro Placement," in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2016), Macau, January 2016.
- M. P.-H. Lin, Y.-W. Chang, and C.-M. Hung, "Recent research development and new challenges in analog layout synthesis," in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2016), Macau, January 2016.
- Z.-W. Lin and Y.-W. Chang, "Double-patterning aware DSA template guided cut redistribution for advanced 1-D gridded designs," in Proceedings of ACM International Symposium on Physical Design (ISPD-2016), Santa Rosa, CA, April 2016.
- C.-C. Huang, Y.-C. Liu, Y.-S. Lu, Y.-C. Kuo, Y.-W. Chang, and S.-Y. Kuo, "Timing-driven cell placement optimization for early slack histogram compression," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2016), Austin, TX, June 2016.
- I.-P. Wu, H.-C. Ou, and Y.-W. Chang, "QB-trees: towards an optimal topological representation with applications to analog layout designs," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2016), Austin, TX, June 2016.
- K.-H. Tseng, Y.-W. Chang, and C. C.-C. Liu, "Minimum-implant-area-aware detailed placement with spacing constraints," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2016), Austin, TX, June 2016.
- Y.-H. Su and Y.-W. Chang, "DSA-compliant routing for two-dimensional patterns using block copolymer lithography," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2016), Austin, TX, November 2016.
- Y.-H. Su and Y.-W. Chang, "VCR: simultaneous via-template and cut-template-aware routing for directed self-Assembly technology," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2016), Austin, TX, November 2016.
- B.-Q. Lin, T.-C. Lin, and Y.-W. Chang, "Redistribution layer routing for integrated fan-out wafer-level chip-scale package," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2016), Austin, TX, November 2016.
- C.-H. Wang, Y.-Y. Wu, J. Chen, Y.-W. Chang, S.-Y. Kuo, W. Zhu, and G. Fan, "An effective legalization algorithm for mixed-cell-height standard cells," in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2016), Tokyo, January 2016.
- Y.-W. Chang, "Generalized force directed relaxation with optimal regions and its applications to circuit placement," in Proceedings of ACM International Symposium on Physical Design (ISPD-2017), Portland, OR, March 2017.
- J. Chen, Z. Zhu, W. Zhu, and Y.-W. Chang, "Toward optimal legalization for mixed-cell-height circuit designs," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2017), Austin, TX, June 2017 (Best Paper Award).
- Y.-C. Huang and Y.-W. Chang, "Fogging effect aware placement in electron beam lithography," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2017), Austin, TX, June 2017.
- C.-C. Huang, B.-Q. Lin, H.-Y. Lee, Y.-W. Chang, K.-Sheng Wu, and J.-Z. Yang, "Graph-based logic bit slicing for datapath-aware placement," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2017), Austin, TX, June 2017
- Z.-W. Lin and Y.-W. Chang, "Detailed placement for two-dimensional directed self-assembly technology," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2017), Austin, TX, June 2017.
- Y.-Y. Wu and Y.-W. Chang, "Mixed-Cell-Height Detailed Placement Considering Complex Minimum-Implant-Area Constraints," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2017) , Irvine, CA, Nov. 2017 (Best-in-Track Paper).
- Y.-C. Kuo), C.-C. Huan), S.-C. Chen, C.-H. Chiang, Y.-W. Chang, and S.-Y. Kuo,"Clock-aware placement for large-scale heterogeneous FPGAs," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2017) , Irvine, CA, Nov. 2017 (Best-in-Track Paper).
- T.-C. Lin, C.-C. Chi and Y.-W. Chang, "Redistribution layer routing for wafer-level integrated fan-out package-on-packages,"
in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2017) , Irvine, CA, Nov. 2017.
- S.-T. Chen, Y.-W. Chang, and T.-C. Chen, "An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2017) , Irvine, CA, Nov. 2017.
- C.-H. Chang, Y.-W. Chang, and T.-C. Chen, "A novel damped-wave framework for macro placement," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2017) , Irvine, CA, Nov. 2017.
- S.-W. Yang, Y.-W. Chang, and T.-C. Chen, "Blockage-aware terminal propagation for placement wirelength minimization,"
in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2017) , Irvine, CA, Nov. 2017
- S.-C. Chen and Y.-W. Chang, "FPGA placement and routing," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2017) , Irvine, CA, Nov. 2017.
- Y.-S. Lu, Y.-H. Chang, and Y.-W. Chang, "WB-trees: a topological representation for FinFET-based analog layout designs," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2018), San Francisco, CA, June 2018 (Best Paper Nominee).
- H.-J. Yu and Y.-W. Chang, "DSA-friendly detailed routing considering double patterning and DSA template assignments," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2018), San Francisco, CA, June 2018.
- Z. Zhu, J. Chen, Z. Peng, W. Zhu, and Y.-W. Chang, "Generalized augmented Lagrangian and its Applications to VLSI global placement," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2018), San Francisco, CA, June 2018.
- R.-Y. Wang, J.-J. Wang, H.-T. Wen, C.-C. Pai, Y.-C. Pai, Y.-W. Chang, C.-M. Lee, and J.-H. Jiang, "Efficient multi-layer obstacle-avoiding region-to-region rectilinear Steiner tree construction," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2018), San Francisco, CA, June 2018.
- Other Conference Papers/Reports:
- Y.-D. Chang, G.-M. Wu, and Y.-W. Chang,
"Can FPD switch matrices be universal?,"
The 8th VLSI Design/CAD Symposium,
pp. 253-256, Nangtou, Taiwan, Aug. 1997.
- Y.-D. Chang, Y.-W. Chang, and M. Shyu,
"Design and analysis of universal switch modules for hierarchical FPGAs,"
in Proceedings of the 9th VLSI Design/CAD Symposium,
Nangtou, Taiwan, Aug. 1998.
- Y.-W. Chang and J.-M. Lin,
"Channel segmentation design for FPGAs,"
in Proceedings of the 9th VLSI Design/CAD Symposium,
Nangtou, Taiwan, Aug. 1998.
- J.-M. Lin, S.-R. Pan, and Y.-W. Chang,
``A timing-driven matching-based algorithm for array-based FPGA routing,"
in Proceedings of the 10th VLSI Design/CAD Symposium,
Nangtou, Taiwan, Aug. 1999.
- H.-R. Jiang, S.-R. Pan, Y.-W. Chang, and J.-Y. Jou,
``Reliable crosstalk-driven interconnect optimization in the deep
submicron technology,"
in Proceedings of the 10th VLSI Design/CAD Symposium,
Nangtou, Taiwan, Aug. 1999.
(Received the 2nd highest score out of the 101 papers and the highest score in the CAD track; score = 3.67 based on 4.0.)
- G.-M. Wu, J.-M. Lin, M. C.-T. Chao, and Y.-W. Chang,
``Generic ILP-based approaches for time-multiplexed FPGA partitioning,"
in Proceedings of The 11th VLSI Design/CAD Symposium,
Pingdong, Taiwan, Aug. 2000.
- G.-M. Wu and Y.-W. Chang,
``Precedence-constrained placement for dynamically reconfigurable FPGAs,"
in Proceedings of The 11th VLSI Design/CAD Symposium,
Pingdong, Taiwan, Aug. 2000.
- S.-R. Pan and Y.-W. Chang,
``Performance optimization by wire/buffer sizing under the transmission
line model,"
in Proceedings of The 11th VLSI Design/CAD Symposium,
Pingdong, Taiwan, Aug. 2000.
- C.-Y. Chang, Y.-W. Chang, and I. H.-R. Jiang,
``Simultaneous buffer-insertion/-sizing and wire-sizing formulae
with applications to
interconnect-driven floorplanning,"
in Proceedings of The 11th VLSI Design/CAD Symposium,
Pingdong, Taiwan, Aug. 2000.
(Received Best Student Paper Award; two out of 125 papers were selected.)
- S.-M. Li, Y.-H. Cherng, and Y.-W. Chang,
``Buffer insertion for noise-aware interconnect-driven floorplanning,"
in Proceedings of The 12th VLSI Design/CAD Symposium,
Hsinchu, Taiwan, Aug. 2001.
- J.-M. Lin, S.-P. Lin, and Y.-W. Chang,
``A P-admissible non-slicing floorplan representation with a
worst-case linear-time packing scheme,"
in Proceedings of The 12th VLSI Design/CAD Symposium,
Hsinchu, Taiwan, Aug. 2001.
(Received the highest score out of 152 papers.)
- S.-C. Lee, J.-M. Hsu, and Y.-W. Chang,
``Multilevel large-scale module placement/floorplanning using
B*-trees,"
in Proceedings of The 12th VLSI Design/CAD Symposium,
Hsinchu, Taiwan, Aug. 2001.
- S.-W. Tu, W.-Z. Shen, Y.-W. Chang, and T.-C. Chen,
``Inductance modeling for on-chip interconnects,"
in Proceedings of The 12th VLSI Design/CAD Symposium,
Hsinchu, Taiwan, Aug. 2001.
- Y.-H. Cheng, Y.-W. Chang and R.-H. Chuang,
``Integrating Buffer Planning with Floorplanning for Simultaneous
Area, Timing, Noise, and Congestion Optimization,"
in Proceedings of The 13th VLSI Design/CAD Symposium,
Taitung, Taiwan, Aug. 2002.
(Received the highest score out of 182 papers; score = 4.0 based on 4.0.)
- S.-P. Lin and Y.-W. Chang,
``A performance-driven multilevel router,"
in Proceedings of The 13th VLSI Design/CAD Symposium,
Taitung, Taiwan, Aug. 2002.
(Received the 2nd highest score out of 182 papers; score = 3.5 based on 4.0.)
- H.-E. Yi, Y.-W. Chang, and M.-C. Wu,
``A B*-tree Based Placer for Boundary Modules,"
in Proceedings of The 13th VLSI Design/CAD Symposium,
Taitung, Taiwan, Aug. 2002.
- Y.-W. Chang, L.-G. Chen, C.-W. Jen, and M.-C. Lan,
``The VLSI Circuits and Systems Education Program in Taiwan,"
to appear in Proceedings of 2003 International Conference on Engineering Education,
Valencia, Spain, July 2003.
- S.-W. Tu, J.-Y. Jou, and Y.-W. Chang, "Layout Techniques for
Minimizing On-Chip Interconnect Inductance,"
The 14th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2003.
- M.-C. Wu and Y.-W. Chang, "Placement with an Optimal Evaluation
Scheme for Alignment and Performance Constraints Using B*-trees,"
The 14th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2003.
- T.-Y. Ho, Y.-W. Chang, and S.-J. Chen,
"A fast crosstalk-driven multilevel routing system,"
The 14th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2003.
- S.-L. Wang and Y.-W. Chang,
"Accurate Delay Formulae for Buffered RLC Trees,"
The 14th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2003.
- T.-C. Chen and Y.-W. Chang,
"Multilevel gridless routing,"
The 15th VLSI Design/CAD Symposium, Pin-Tung, Taiwan, Aug. 2004.
- S.-W. Tu, Y.-W. Chang, and J.-Y. Jou,
"RLC circuit simulation and bus encoding for delay reduction,"
The 15th VLSI Design/CAD Symposium, Pin-Tung, Taiwan, Aug. 2004.
- T.-C. Chen and Y.-W. Chang,
"Fixed-outline floorplanning using the B*-tree representation,"
The 15th VLSI Design/CAD Symposium, Pin-Tung, Taiwan, Aug. 2004.
- C.-Y. Lai, S.-K. Jeng, and Y.-W. Chang,
"Surface integral inductance extraction for general interconnect structures,"
The 15th VLSI Design/CAD Symposium, Pin-Tung, Taiwan, Aug. 2004.
- T.-C. Chen and Y.-W. Chang,
"Full-chip gridless routing using a novel multilevel framework,"
The 16th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2005.
- K. S.-M. Li, C.-L. Lee, Y.-W. Chang, C.-C. Su, and J. E. Chen,
"Multilevel full-chip routing with testability and yield enhancement,"
The 16th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2005.
- J.-W. Fang, I.-J. Lin, and Y.-W. Chang,
"An RDL router for flip-chip design,"
The 16th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2005.
- C.-F. Chang, T.-Y. Ho, and Y.-W. Chang,
"XRoute: a multilevel routing system for the X-based architecture,"
The 16th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2005.
- T.-C. Chen and Y.-W. Chang,
"A new multilevel framework for large-scale interconnect-driven floorplanning,"
The 16th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2005.
- K. S.-M. Li, C.-L. Lee, Y.-W. Chang, C.-C. Su, and J. E. Chen,
"P1500 based interconnect delay and crosstalk fault diagnosis,"
The 16th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2005.
- T.-C. Chen, P.-H. Yuh, Y.-W. Chang, F.-J. Huang, and D. Liu,
"A Macro Placer Based on a New Packing Representation,"
The 17th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2006.
- T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang,
"A Novel Analytical Mixed-Size Placement Algorithm Considering Preplaced Blocks,"
The 17th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2006.
- W.-P. Lee, H.-Y. Liu, and Y.-W. Chang,
"Timing-Constrained Voltage Island Assignment and Floorplanning for Power Optimization,"
The 17th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2006.
- T.-Y. Ling, I-J. Lin, and Y.-W. Chang,
"A Statistical Circuit Optimization Algorithm under Thermal and Timing Constraints,"
The 17th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2006.
- S.-J. Chou, C.-H. Hsu, J.-H. Jiang, and Y.-W. Chang,
"Statistical Timing-Yield Optimization via Latch Substitution,"
The 17th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2006.
- P.-H. Yuh, C.-L. Yang, and Y.-W. Chang, "BioRoute: A network-flow
based routing algorithm for digital microfluidic biochips,"
The 18th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2007.
(Best Paper Award; Received the highest score in the EDA category; the first year awarding best papers after 2000)
- T.-C. Chen, G.-W. Liao, and Y.-W. Chang, "Lithography-aware routing
with predictive OPC formulae," The 18th VLSI Design/CAD Symposium,
Hua-Lien, Taiwan, Aug. 2007.
- H.-C. Chen, Y.-L. Chuang, and Y.-W. Chang, "A high quality
transitive-closure-graph-based macro placer,"
The 18th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2007.
- C.-H. Hsu, H.-Y. Chen, and Y.-W. Chang, "Fast global routing with forbidden-region rerouting,"
The 19th VLSI Design/CAD Symposium, Ping-Tong, Taiwan, Aug. 2008.
- C.-H. Hsu, H.-Y. Chen, and Y.-W. Chang, "Global routing with via/wire capacity considerations,"
The 19th VLSI Design/CAD Symposium, Ping-Tong, Taiwan, Aug. 2008.
- H.-Y. Chen, S.-J. Chou, and Y.-W. Chang, "Coupling-constrained dummy fill for density gradient minimization,"
The 19th VLSI Design/CAD Symposium, Ping-Tong, Taiwan, Aug. 2008.
(Best Paper Award)
- P.-W. Lee, C.-W. Lin, and Y.-W. Chang, "Fast pre-assignment flip-chip routing,"
The 20th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2009. (Best Paper Nominee; best paper award selection was cancelled due to typhoon Morakot)
- X.-W. Shih, C.-C. Cheng, Y.-K. Ho, and Y.-W. Chang, "NTUclock: A high-quality
blockage-avoiding buffered clock-tree router for modern circuit designs,"
The 20th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2009.
- T.-F. Chien, W.-C. Chao, Chien-Mo Li, K.-Y. Liao, Y.-W. Chang, M.-T. Chang, M.-H. Tsai, and C.-M. Tseng,
"SoC memory BIST design optimization,"
The 20th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2009.
- K.-H. Ho, J.-H. Jiang, and Y.-W. Chang, "Technology remapping for ECO timing optimization,"
The 20th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2009.
- S.-Y. Fang, T.-F. Chien, and Y.-W. Chang, "ECO timing and mask-cost optimization with Redundant wires," in the 21st VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 2010. (Best Paper Award)
- K.-H. Ho, X.-W. Shih, S.-H. Chuang, J.-H. Jiang, and Y.-W. Chang, "ECO Timing Optimization using Clock Rescheduling," in the 21st VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 2010. (Best Paper Nominee)
- M.-K. Hsu and Y.-W. Chang, "Unified analytical approach for mixed-size global placement," in the 21st VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 2010. (Best Paper Nominee)
- M.-K. Hau, S. chou, T.-H. Lin, and Y.-W. Chang, "A novel routability-driven analytical placement algorithm," in the 22nd VLSI Design/CAD Symposium, Yun-Lin, Taiwan, Aug. 2011. (Best Paper Nominee)
- H.-Y. Chang, H.-R. I. Jiang, and Y.-W. Chang, "Cost-effective timing ECO optimization," in the 22nd VLSI Design/CAD Symposium, Yun-Lin, Taiwan, Aug. 2011. (Best Paper Nominee)
- S.-Y. Fang, C.-W. Lin, G.-W. Liao, and Y.-W. Chang, "Accurate closed-form modeling for simultaneous OPC- and CMP-aware routing," in the 23rd VLSI Design/CAD Symposium, Ping-Tong, Taiwan, Aug. 2012.
- T.-H. Lin, P. Banerjee, and Y.-W. Chang, "An efficient analytical placer for FPGA designs," in the 23rd VLSI Design/CAD Symposium, Ping-Tong, Taiwan, Aug. 2012.
- C.-C. Huang, H.-Y. Lee, B.-Q. Lin, S.-W. Yang, C.-H. Chang, S.-T. Chen, and Y.-W. Chang, "A detailed-routability-driven analytical placer considering technology and region constraints," in the 26th VLSI Design/CAD Symposium, Hau-Lien, Taiwan, Aug. 2015. (Best Paper Award)
- Z.-W. Lin and Y.-W. Chang, "DSA Templates Guided Cut Redistribution for Advanced 1-D Gridded Layouts," in the 26th VLSI Design/CAD Symposium, Hau-Lien, Taiwan, Aug. 2015.
- B.-Q. Lin, T.-C. Lin, and Y.-W. Chang, "An effective RDL routing algorithm for the InFO WLCSP technology," in the Proceedings of 27th VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 2016. (Best feature paper award; formerly best paper award)
- C.-H. Wang, Y.-Y. Wu, J. Chen, Y.-W. Chang, S.-Y. Kuo, W. Zhu, and G. Fan, "Legalization for multiple-cell-height standard cells," in the Proceedings of 27th VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 2016.
- Patents:
- T.-C. Chen, Y.-W. Chang, and C.-C. Lin, Multilevel IC Floorplanner, US Patent 7,603,640, October 13, 2009
- C. Lin, T.-C. Chen, Y.-W. Chang, D. Chang, V-Shaped Multilevel Full-Chip Gridless Routing, US Patent 7,707,536, June 2010
- T.-C. Chen, P.-H. Yu, Y.-W. Chang, F.-J. Lin, and D. Liu, Method of packing-based macro placement and semiconductor chip using the same, Japan and China patents granted (US Patent, Application number: 11/608,417, Publication number: US 2007/0157146 A1)
- C.-H. Hsu and Y.-W. Chang, Method for Concurrent Migration and Decomposition of Integrated Circuit Layout, US Patent pending, 2009
- 陳東傑, 喻秉鴻, 張耀文, 黃福助, and 劉典岳, "半導體晶片、巨集擺置的方法、多向密集堆積巨集擺置器與多尺寸混合擺置設計方法," Taiwan Patent 096100036
- X.-W. Shih and Y.-W. Chang, Clock-tree structure and method for synthesizing the same, US Patent US 8,572,542, Sept. 2013.
- 施信瑋 and 張耀文, "時鐘樹結構及其合成方法," Taiwan Patent 099136896.
- H.-Y. Chen and Y.-W. Chang, Layout Decomposition Method Applicable to Double Patterning Lithography, US Patent pending, 2010 (Taiwan patent granted: I 397868)
- 張耀文 and 陳皇宇, 應用於雙圖案微影技術的佈局分解方法 (Method for resolving layout and configured for use with dual-pattern lithography), 中華民國專利, I 397828, June 13, 2013.
- V. Balabanov, H.-K. Hsu, and Y.-W. Chang, Method of Analytical Placement with Weighted-Average Wirelength Model, US Patent 8,689,164, April 2014.
- 包偉力, 徐孟楷, 張耀文, 以加權平均線長模型實現之解析配置演算法, 中華民國專利, I430127, March 11, 2014.
- 張華宇, 江蕙如, 張耀文, 時序設計變更的方法 (Method of implementing timing engineering change order), 中華民國專利, Application Number: 101128031.
- 張宸峰, 沈勤芳, 邱顥仕, 林依潔, 許天彰, 張耀文, 林忠緯, 李柏緯, 覆晶封裝之繞線方法及其電腦化裝置 (Routing method for flip chip package and the computerized apparatus using the same), 中華民國專利, Application Number: 201122876.
- C.-F. Chang, C.-F. Shen, H.-S. Chiu, I-J. Lin, T.-C. Hsu, Y.-W. Chang, C.-W. Lin, and P.-W. Lee, Routing method for flip chip package and the computerized apparatus using the same, US Patent Granted, Application Number: US20120216167.
- 張宸峰, 沈勤芳, 邱顥仕, 林依潔, 許天彰, 張耀文, 林忠緯, 李柏緯, 應用於單層繞線軌跡之分析方法及其電腦化裝置 (Method for analyzing single layer routing tracks and the computerized apparatus using the same), 中華民國專利, Application Number: 201122881.
- H.-Y. Chang, H.-R. Jiang, and Y.-W. Chang, Method of implementing timing engineering change order, US Patent 8,776,000, July 8, 2014
- I.-P. Wu, H.-C. Ou, Y.-W. Chang, and Y.-C. Hsieh, Method for analog circuit placement, US Patent Granted, App. No: 15/002.385, Dec. 2017.
- B.-Q. Lin, T.-C. Lin, C.-Y. Yang, and Y.-W. Chang, Redistribution layer routing for integrated fan-out wafer-level chip-scale packages, US Patent US 2018/0032660 A1, Feb. 2018.
- Technical Reports:
- Y.-W. Chang, D. F. Wong, and C. K. Wong,
``Universal switch modules for FPGA design,''
Dept. of Computer Sciences,
University of Texas at Austin,
TR95-27, August 1995.
- Y.-W. Chang, K. Zhu, D. F. Wong, and C. K. Wong,
``Analysis of FPGA/FPIC switch modules,''
Dept. of Computer Sciences,
University of Texas at Austin,
TR96-32, September 1996.
- Y.-W. Chang, H.-R. Jiang, and J.-Y. Jou,
``Lagrangian relaxation for post-layout optimization for SoC design,''
Engineering Science & Technology Bulletin, National Science Council,
pp. 130-133, September 2001.
- Dissertation:
- Other Articles:
- Y.-W. Chang, "Ansel Adams--Master of the Straight Photography (in Chinese)," Light & Shadows, No. 6, June 1985.
- Y.-W. Chang, "Introduction to photography (in Chinese)," Light & Shadows, No. 13, April 1987.
- Y.-W. Chang, "Thoughts on the meanings of images (in Chinese)," Light & Shadows, No. 17,
May 1988.