Publications

Publications

ACM/IEEE Journal Papers:
1. Y.-W. Chang, D. F. Wong, and C. K. Wong, ``Universal switch modules for FPGA design,'' ACM Trans. on Design Automation of Electronic Systems (TODAES), Vol. 1, No. 1, pp. 80--101, January 1996.
  See an implementation report for our universal switch modules from Dept. of EECS, Univ. of California at Berkeley.
2. S. Thakur, Y.-W. Chang, D. F. Wong, and S. Muthukrishnan, ``Algorithms for an FPGA switch module routing problem with application to global routing,'' IEEE Trans. on Computer-Aided Design (TCAD), Vol. 16, No. 1, pp. 32--47, January 1997.
3. G.-M. Wu and Y.-W. Chang, "Quasi-universal switch matrices for FPD design," in IEEE Trans. on Computers (TC), Vol. 48, No. 10, pp. 1107-1122, Oct. 1999.
4. M. Shyu, Y.-D. Chang, G.-M. Wu, and Y.-W. Chang, "Generic universal switch blocks," in IEEE Trans. on Computers (TC), vol. 49, no. 4, pp. 348--359, April 2000.
5. Y.-W. Chang, K. Zhu, and D. F. Wong, ``Timing-driven routing for symmetrical-array-based FPGAs,'' ACM Trans. on Design Automation of Electronic Systems, Vol. 5, No. 3, pp. 433--450, July 2000.
6. H.-R. Jiang, Y.-W. Chang, and J.-Y. Jou, "Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing," IEEE Trans. on Computer-Aided Design, Vol. 19, No. 9, pp. 999--1010, September 2000.
7. Y.-W. Chang, J.-M. Lin, and D. F. Wong, "A matching-based algorithm for FPGA channel segmentation design," in IEEE Trans. Computer-Aided Design, Vol. 20, No. 6, pp. 784--791, June 2001.
8. G.-M. Wu, J.-M. Lin, and Y.-W. Chang, ``Generic ILP-based approaches for time-multiplexed FPGA partitioning," in IEEE Trans. Computer-Aided Design, Vol. 20, No. 10, pp. 1266--1274, October 2001.
9. H. Fang, Y.-L. Wu, and Y.-W. Chang, "Comments on "Generic universal switch blocks"," in IEEE Trans. on Computers (TC), vol. 51, no.1, pp. 93--95, 2002.
10. G.-M. Wu, J.-M. Lin, and Y.-W. Chang, ``Performance-driven placement for dynamically reconfigurable FPGAs," in ACM Trans. on Design Automation of Electronic Systems, Vol. 7, No. 4, pp. 628--642, October 2002.
11. J.-M. Lin, H.-L. Lin, and Y.-W. Chang, ``Arbitrarily shaped rectilinear module placement using the transitive closure graph representation," in IEEE Trans. VLSI Systems, Vol. 10, No. 6, pp. 886--901, December 2002.
12. Y.-W. Chang, K. Zhu, D. F. Wong, G.-M. Wu, and C. K. Wong, ``Analysis of FPGA/FPIC switch modules,'' in ACM Trans. on Design Automation of Electronic Systems, Vol. 8, No. 1, pp. 11-37, January 2003.
13. G.-M. Wu, Y.-C. Chang, and Y.-W. Chang, ``Rectilinear block placement using B*-trees," ACM Trans. on Design Automation of Electronic Systems, Vol. 8., No. 2, pp. 188--202, April 2003. (Best Paper Nominee)
14. J.-M. Lin, Y.-W. Chang, and S.-P. Lin, "Corner sequence: A P-admissible floorplan representation with a worst-case linear-time packing scheme," IEEE Trans. VLSI Systems, Vol. 11, No. 4, pp. 679--686, August 2003.
15. T.-C. Chen, S.-R. Pan, and Y.-W. Chang, ``Timing modeling and optimization under the transmission line model," IEEE Trans. VLSI Systems, Vol. 12, No. 1, pp. 28--41, January 2004.
16. Y.-W. Chang and S.-P. Lin, "MR: A New Framework for Multilevel Full-Chip Routing," IEEE Trans. Computer-Aided Design, Vol. 23, No. 5, pp. 793--800, May 2004.
17. H.-R. Jiang, Y.-W. Chang, J.-Y. Jou, K.-Y. Chao, ``Simultaneous Floorplanning and Buffer Block Planning," in IEEE Trans. Computer-Aided Design, Vol. 23, No. 5, pp. 694--703, May 2004.
18. J.-M. Lin and Y.-W. Chang, ``TCG-S: Orthogonal Coupling of P*-admissible Representations for General Floorplans," IEEE Trans. Computer-Aided Design, Vol. 23, No. 6, pp. 968--980, June 2004.
19. J.-M. Lin and Y.-W. Chang, ``TCG: A transitive closure graph based representation for general floorplans," in IEEE Trans. VLSI Systems, Vol. 13, No. 2, pp. 288--292, February 2005.
20. T.-Y. Ho, Y.-W. Chang, S.-J. Chen, and D. T. Lee, "Crosstalk-and performance-driven multilevel full-chip routing," in IEEE Trans. Computer-Aided Design, Vol. 24, No. 6, pp. 869--878, June 2005.
21. H.-R. Jiang, S.-R., Pan, Y.-W. Chang, and J.-Y. Jou, ``Reliable Crosstalk-driven interconnect optimization," in ACM Trans. on Design Automation of Electronic Systems, Vol. 11, No. 1, January 2006.
22. T.-C. Chen and Y.-W. Chang, ``Modern Floorplanning Based on B*-trees and Fast Simulated Annealing," in IEEE Trans. Computer-Aided Design, Vol. 25, No. 4, pp. 637--650, April 2006.
23. S.-W. Tu, J.-Y. Jou, and Y.-W. Chang, ``RLC coupling-aware simulation and on-chip bus encoding for delay reduction," in IEEE Trans. Computer-Aided Design, Vol. 25, No. 10, pp. 2258--2264, October 2006.
24. K. S.-M. Li, C.-C. Su, Y.-W. Chang, C.-L. Lee, and J. E Chen, ``P1500 Standard Compatible Interconnect Diagnosis for Delay and Crosstalk Faults, in IEEE Trans. Computer-Aided Design, Vol. 25, No. 11, pp. 2513--2525, November 2006.
25. C.-W. Liu and Y.-W. Chang, "Power/ground network and floorplan co-synthesis for fast design convergence," in IEEE Trans. Computer-Aided Design, Vol. 26, No. 4, pp. 693--704, April 2007.
26. B.-Y. Su, Y.-W. Chang, and J. Hu, ``An exact jumper insertion algorithm for antenna violation avoidance/fixing considering routing obstacles," in IEEE Trans. Computer-Aided Design, Vol. 26, No. 4, pp. 719--734, April 2007.
27. T.-C. Chen and Y.-W. Chang, "Multilevel full-chip gridless routing with applications to optical proximity correction," in IEEE Trans. Computer-Aided Design, Vol. 26, No. 6, pp. 1041--1053, June 2007.
28. H.-C. Lee, Y.-W. Chang, and H. Yang, ``MB*-tree: A multilevel floorplanner for large-scale building-module design," in IEEE Trans. Computer-Aided Design, Vol. 26, No. 8, pp. 1430--1444, August 2007.
29. J.-W. Fang, I.-J. Lin, Y.-W. Chang, and J.-H. Wang, " A network-flow based RDL routing algorithm for flip chip design," in IEEE Trans. Computer-Aided Design, Vol. 26, No. 8, pp. pp. 1417--1429, August 2007.
30. K. S.-M. Li, C.-L. Lee, Y.-W. Chang, C.-C. Su, and J. E Chen, ``Multilevel full-chip routing with testability and yield enhancement", in IEEE Trans. Computer-Aided Design, Vol. 26, No. 9, pp. 1625--1636, September 2007.
31. P.-H. Yu, C.-L. Yang, and Y.-W. Chang, ``Temporal floorplanning using the three-dimensional transitive closure subgraph," in ACM Trans. Design Automation of Electronic Systems, Vol. 12, No. 4, September 2007 (34 pages).
32. B.-Y. Su and Y.-W. Chang, ``An optimal jumper insertion algorithm for antenna avoidance/fixing ," in IEEE Trans. Computer-Aided Design, Vol. 26, No. 10, pp. 1818--1929, October 2007.
33. P.-H. Yu, C.-L. Yang, and Y.-W. Chang, "Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation," in ACM Journal of Emerging Technologies in Computing Systems (JETC), Vol. 3, No. 3, November 2007 (32 pages).
34. T.-C. Chen, Y.-W. Chang, and S.-C. Lin, "A new multilevel framework for large-scale interconnect-driven floorplanning," in IEEE Trans. Computer-Aided Design, Vol. 27, No. 2, pp. 286--294, February 2008.
35. C.-W. Lin, S.-Y. Chen, C.-F. Li, Y.-W. Chang, and C.-L. Yang, ``Obstacle-avoiding rectilinear Steiner tree construction based on spanning graphs ," in IEEE Trans. Computer-Aided Design, Vol. 27, No. 4, pp. 643--653, April 2008.
36. T.-C. Chen, Y.-L. Chuang, and Y.-W. Chang, ``Effective wire models for X-architecture placement ," in IEEE Trans. Computer-Aided Design, Vol. 27, No. 4, pp. 654--658, April 2008.
37. H.-Y. Chen, M.-F. Chiang, Y.-W. Chang, L. Chen, and B. Han, "Full-chip routing considering double-via insertion," in IEEE Trans. Computer-Aided Design, Vol. 27, No. 5, pp. 844--857, May 2008.
38. Z.-W. Jiang and Y.-W. Chang, "An optimal network-flow-based simultaneous diode and jumper insertion algorithm for antenna fixing," in IEEE Trans. Computer-Aided Design, Vol. 27, No. 6, pp. 1055--1065, June 2008.
39. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, "NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints," in IEEE Trans. Computer-Aided Design, Vol. 27, No. 7, pp. 1228--1240, July 2008.
40. C.-H. Liu, H.-Y. Liu, C.-W. Lin, S.-J. Chou, Y.-W. Chang, S.-Y. Kuo, and S.-Y. Yuan, "An efficient graph-based algorithm for ESD current path analysis," in IEEE Trans. Computer-Aided Design, Vol. 27, No. 8, pp. 1363--1375, August 2008.
41. T.-C. Chen, P.-H. Yuh, Y.-W. Chang, F.-J. Huang, and D. Liu, " MP-trees: A packing-based macro placement algorithm for modern mixed-size designs," to appear in IEEE Trans. Computer-Aided Design, Vol. 27, No. 9, pp. 1621--1634, September 2008.
42. C.-W. Lin, S.-L. Huang, K.-C. Hsu, M.-X. Li, and Y.-W. Chang, "Multi-layer obstacle-avoiding rectilinear Steiner tree construction based on spanning graphs," in IEEE Trans. Computer-Aided Design, Vol. 27, No. 11, pp. 2007--2016, November 2008.
43. P.-H. Yu, C.-L. Yang, and Y.-W. Chang, "BioRoute: a network-flow based routing algorithm for the synthesis of digital microfluidic biochips," in IEEE Trans. Computer-Aided Design, Vol. 27, No. 11, pp. 1928--1941, November 2008.
44. T.-C. Chen, M. Cho, D. Z. Pan, and Y.-W. Chang, "Metal-density driven placement for CMP variation and routability," IEEE Trans. Computer-Aided Design, Vol. 27, No. 12, pp. 2145--2155, December 2008.
45. J.-W. Fang, C.-H. Hsu, and Y.-W. Chang, "An integer linear programming based routing algorithm for flip-chip designs," IEEE Trans. Computer-Aided Design, Vol. 28, No. 1, pp. 98--110, January 2009.
46. H.-Y. Chen, S.-J. Chou, S.-L. Wang, and Y.-W. Chang, "A novel wire-density-driven full-chip routing system for CMP variation control," IEEE Trans. Computer-Aided Design, Vol. 28, No. 2, pp. 193--206, February 2009.
47. W.-P. Lee, H.-Y. Liu, and Y.-W. Chang, "Voltage island partitioning and floorplanning under timing constraints," in IEEE Trans. Computer-Aided Design, Vol. 28, No. 5, pp. 690--702, May 2009.
48. P.-H. Lin, Y.-W. Chang, and S.-C. Lin, "Analog placement based on symmetry-island and tree formulation," in IEEE Trans. Computer-Aided Design, Vol. 28, No. 6, pp. 791--804, June 2009.
49. P.-H. Yu, S. Sapatnekar, C.-L. Yang, and Y.-W. Chang, "A progressive-ILP based routing algorithm for cross-referencing biochips," in IEEE Trans. Computer-Aided Design, Vol. 28, No. 9, pp. 1295--1306, Sept. 2009.
50. H.-Y. Chen and Y.-W. Chang, "Routing for manufacturability and reliability," in IEEE Circuits and Systems Magazine, pp. 20--31, September 2009 (invited feature article).
51. P.-H. Yu, C.-L. Yang, and Y.-W. Chang, "T-trees: A Tree-Based Representation for Temporal Floorplanning," to appear in ACM Trans. Design Automation of Electronic Systems, 2009.
52. T.-C. Chen, G.-W. Liao, and Y.-W. Chang, "Predictive formulae for OPC with applications to lithography-friendly routing," to appear in IEEE Trans. Computer-Aided Design, Vol. 29, No. 1, January 2010.
53. J.-W. Fang and Y.-W. Chang, "Area-I/O flip-chip routing for chip-package co-design considering signal skews," in revision, IEEE Trans. Computer-Aided Design, 2010.
54. C.-Y. Lin and Y.-W. Chang, "ILP-based pin-count aware design methodology for microfluidic biochips," in revision, IEEE Trans. Computer-Aided Design, 2010.
55. C.-H. Hsu, H.-Y. Chen, and Y.-W. Chang, "Multi-layer global routing with via and wire capacity considerations," in revision, IEEE Trans. Computer-Aided Design, 2010.
56. K.-H. Ho, Y.-P. chen, J.-W. Fang, and Y.-W. Chang, "ECO timing optimization using spare cells and technology remapping," in revision, IEEE Trans. Computer-Aided Design, 2010.
Other Journal Papers:
1. J.-M. Lin, H.-E. Yi, and Y.-W. Chang, "Module placement with boundary constraints using B*-trees," in IEE Proceedings--Circuits, Devices and Systems, Vol. 149, No. 4, pp. 251--256, August 2002. (EI/SCI)
2. Y.-M. Lee, C.-P. Chen, Y.-W. Chang, and D.-F. Wong, "Simultaneous buffer-sizing and wire-sizing for clock trees based on Lagrangian relaxation," VLSI Design, Vol. 15, No. 3, pp. 587--594, November 2002 (invited paper). (EI/SCI)
3. S.-W. Tu, W.-Z. Shen, Y.-W. Chang, T.-C. Chen, and J.-Y. Jou, "Inductance modeling for on-chip interconnects," in International Journal of Analog Integrated Circuits and Signal Processing, Vol. 35, No. 1, pp. 65--78, April 2003 (invited paper). (EI/SCI)
4. G.-M. Wu, M. Shyu, and Y.-W. Chang, "Universal switch blocks for three-dimensional FPGA design," in IEE Proceedings---Circuits, Devices, and Systems, Vol. 151, No. 1, pp. 49-57, February 2004. (EI/SCI)
5. G.-M. Wu, C.-T. M. Chao, and Y.-W. Chang, "A clustering and probability based partitioning algorithm for time-multiplexed FPGAs," in Integration: The VLSI Journal, Vol. 38, Issue 2, pp. 245-265, December 2004 (EI/SCI).
6. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, Multilevel Routing with Jumper Insertion for Antenna Avoidance, Integration: The VLSI Journal, Volume 39, Issue 4, pp. 420--432, July 2006 (EI/SCI).
7. Y.-W. Chang, Z.-W. Jiang, and T.-C. Chen, "Essential issues in analytical placement algorithms," IPSJ Transactions on System LSI Design Methodology, Vol. 2, pp. 145--166, August 2009 (invited paper).
Books and Book Chapters:
1. M. Shyu, M.-H. Shieh, Y.-T. Chang, W.-H. Shiue, and Y.-W. Chang, The Practical Xilinx Designer Lab Book (translation in Chinese), Chuan-Hwa Science & Technology Book Co., 480 pages, Nov. 1998.
2. Y.-W. Chang, D. F. Wong, and C. K. Wong, ``Programmable logic arrays'' in Encyclopedia of Electrical and Electronics Engineering (John G. Webster, Editor), John Wiley & Sons, Vol. 17, pp. 334-348, 1999 (invited article).
3. Y.-W. Chang, T.-C. Chen, and H.-Y. Chen, "Physical Design for System-On-a-Chip" in Essential Issues in SOC Design (Y.-L. Lin, Editor), Springer, pp. 311-403, 2006 (invited article).
4. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, "NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs," (G.-J. Nam and J. Cong, Editors), 2007 (invited article).
5. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, Full-chip Nanometer Routing Techniques, Springer, 2007.
6. F. Y. Young, C.-K. Koh, and Y.-W. Chang, "Buffer planning," in Physical Design Handbook (C. Alpert, S. Sapatnekar, and Dinesh D. Mehta, Editors), CRC Press, 2008 (invited article).
7. T.-C. Chen and Y.-W. Chang, "Packing floorplan representation" in Physical Design Handbook (C. Alpert, S. Sapatnekar, and Dinesh D. Mehta, Editors), CRC Press, 2008 (invited article).
8. L.-T. Wang, Y.-W. Chang, and K.-T. Cheng (editors), Electronic Design Automation: Synthesis, Verification, and Testing, Elsevier/Morgan Kaufmann, 2009 (934 pages).
ACM/IEEE Conference Papers:
1. K. Zhu, D. F. Wong, and Y.-W. Chang, ``Switch module design with application to two-dimensional segmentation design,'' Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 480--485, Santa Clara, CA, Nov. 1993.
2. Y.-W. Chang, S. Thakur, K. Zhu, and D. F. Wong, `` A new global routing algorithm for FPGAs,'' Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 380--385, San Jose, CA, Nov. 1994.
3. Y.-W. Chang, D. F. Wong, and C. K. Wong, ``FPGA global routing based on a new congestion metric,'' Proceedings of IEEE International Conference on Computer Design (ICCD), pp. 372--378, Austin, TX, Oct. 1995. (Best Paper Award.)
4. Y.-W. Chang, D. F. Wong, and C. K. Wong, ``Design and analysis of FPGA/FPIC switch modules,'' Proceedings of IEEE International Conference on Computer Design (ICCD), pp. 394--401, Austin, TX, Oct. 1995.
5. Y.-W. Chang, D. F. Wong, and C. K. Wong, ``Universal switch-module design for symmetrical-array-based FPGAs,'' Proceedings of ACM International Symposium on Field Programmable Gate Arrays (FPGA), pp. 80--86, Monterey, CA, February 1996.
  (Received the highest score.) See an implementation report for our universal switch modules from Dept. of EECS, Univ. of California at Berkeley.
6. Y.-W. Chang, D. F. Wong, K. Zhu, and C. K. Wong, ``On a new timing-driven routing tree problem,'' Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. IV: 420--423, Atlanta, GA, May 1996.
7. C.-P. Chen, Y.-W. Chang, and D. F. Wong, ``Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation,'' Proceedings of 33rd ACM/IEEE Design Automation Conference (DAC), pp. 405--408, Las Vegas, NV, June 1996.
8. Y.-W. Chang, D. F. Wong, and C. K. Wong, ``A graph-theoretic sufficient condition for FPGA/FPIC switch-module routability,'' Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), vol. III, pp. 1572--1575, Hong Kong, June 1997.
9. G.-M. Wu and Y.-W. Chang, "Switch-matrix design and routing for FPDs," Proceedings of ACM International Symposium on Physical Design (ISPD), pp. 158-163, Monterey, CA, April 1998.
10. G.-M. Wu and Y.-W. Chang, "Maximally routable switch matrices for FPD design," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS-98), VI: 131--134, Monterey, CA, May 1998.
11. K. Zhu, Y.-W. Chang, and D. F. Wong, "Timing-driven routing for symmetrical-array-based FPGAs," Proceedings of IEEE International Conference on Computer Design (ICCD-98), pp. 628--633, Austin, TX, October 1998.
12. Y.-W. Chang, J.-M. Lin, and D. F. Wong, "Graph matching-based algorithms for FPGA segmentation design," Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-98), pp. 34-39, Santa Clara, Nov. 1998.
13. G.-M. Wu, M. Shyu, and Y.-W. Chang, ``Universal switch blocks for three-dimensional FPGA design,'' presented at 1999 ACM International Symposium on Field Programmable Gate Arrays (FPGA-99) (poster), Monterey, CA, February 1999.
  This work was cited by the article FPGA'99: Advanced processes unleash architectural ideas in the EE Times weekly, February 23, 1999.
14. H.-R. Jiang, J.-Y. Jou, and Y.-W. Chang, ``Noise-constrained performance optimization by gate and wire sizing based on Lagrangian relaxation,'' in Proc. of ACM/IEEE Design Automation Conference (DAC-99), pp. 90-95, New Orleans, LA, June 1999.
15. M. Shyu, Y.-D. Chang, G.-M. Wu, and Y.-W. Chang, ``Generic universal switch-block architectures and their interactions with routing,'' in Proc. of IEEE International Conference on Computer Design (ICCD-99), pp. 311-314, Austin, TX, Oct. 1999.
16. C.-T. M. Chao, G.-M. Wu, H.-R. Jiang, and Y.-W. Chang, ``A clustering and probability based partitioning algorithm for time-multiplexed FPGAs," in Proc. of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-99), pp. 364-368, Santa Clara, CA, Nov. 1999.
17. H.-R. Jiang, S.-R., Pan, Y.-W. Chang, and J.-Y. Jou, ``Reliable crosstalk-driven interconnect optimization," in Proc. of ACM International Symposium on Physical Design (ISPD-2000), pp. 128-133, San Diego, CA, Apr. 2000.
18. Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu, ``B*-trees: A new representation for non-slicing floorplans," in Proc. of ACM/IEEE Design Automation Conference (DAC-2000), pp. 458-463, LA, CA, June 2000. (Best Paper Nominee)
19. Y.-W. Chang and Y.-T. Chang, ``An architecture-driven metric for simultaneous placement and routing for FPGAs," in Proc. of ACM/IEEE Design Automation Conference (DAC-2000), pp. 567-572, LA, CA, June 2000.
20. G.-M. Wu, Y.-C. Chang, and Y.-W. Chang, ``Rectilinear block placement using B*-trees," in Proc. of IEEE International Conference on Computer Design (ICCD-00), pp. 351-356, Austin, TX, Oct. 2000.
21. S.-R. Pan and Y.-W. Chang, ``Crosstalk-constrained Performance Optimization by Using Wire Sizing and Perturbation," in Proc. of IEEE International Conference on Computer Design (ICCD-00), pp. 581-584, Austin, TX, Oct. 2000.
22. J.-M. Lin and Y.-W. Chang, ``TCG: A transitive closure graph based representation for non-slicing floorplans," in Proc. of ACM/IEEE Design Automation Conference (DAC-2001), pp. 764--769, Las Vegas, NV, June 2001.
23. T.-C. Chen, S.-R. Pan, and Y.-W. Chang, ``Performance optimization by wire and buffer sizing under the transmission line model," in Proc. of IEEE International Conference on Computer Design (ICCD-01), pp. 192--197, Austin, TX, Nov. 2001.
24. G.-M. Wu, J.-M. Lin, M. C.-T. Chao, and Y.-W. Chang, ``Generic ILP-based approaches for dynamically reconfigurable FPGA partitioning ," in Proc. of IEEE International Conference on Computer Design (ICCD-01), pp. 335--340, Austin, TX, Nov. 2001. (Best Paper Nominee)
25. G.-M. Wu and Y.-W. Chang, ``An Algorithm for Dynamically Reconfigurable FPGA Placement," in Proc. of IEEE International Conference on Computer Design (ICCD-01), pp. 501--504, Austin, TX, Nov. 2001.
26. C.-Y. Chang, H.-R. Jiang, and Y.-W. Chang, "Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning," in 2002 IEEE International Symposium on Quality of Electronic Design (ISQED 2002), pp. 523--528, San Jose, CA, March 2002.
27. J.-M. Lin, H.-L. Lin, and Y.-W. Chang, ``Arbitrary Convex and Concave Rectilinear Module Packing Using TCG," in Proc. of ACM/IEEE Design Automation and Test in Europe (DATE-2002), pp. 69--75, Paris, France, March 2002.
28. S.-W. Tu, W.-Z. Shen, Y.-W. Chang, and T.-C. Chen, ``Inductance modeling for on-chip interconnects," in Proceedings of the IEEE Symposium on Circuits and Systems (ISCAS-2002), vol. 3, pp. 787--790, Pheonix, AZ, May 2002.
29. J.-M. Lin and Y.-W. Chang, ``TCG-S: Orthogonal Coupling of P*-admissible Representations for General Floorplans," in Proc. of ACM/IEEE Design Automation Conference (DAC-2002), pp. 842--847, New Orleans, June 2002.
30. S.-P. Lin and Y.-W. Chang, "A novel framework for multilevel routing considering routability and performance," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2002), pp. 44--50, San Jose, Nov. 2002. (Best Paper Nominee)
31. S.-M. Li, Y.-H. Cherng, and Y.-W. Chang, ``Noise-aware buffer planning for interconnect-driven floorplanning," in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2003), pp. 423--426, Kitakyushu, Japan, January. 2003.
32. H.-R. Jiang, Y.-W. Chang, J.-Y. Jou, and K.-Y. Chao, ``Simultaneous Floorplanning and Buffer Block Planning," in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2003), pp. 431--434, Kitakyushu, Japan, January. 2003.
33. J.-M. Lin, S.-R. Pan, and Y.-W. Chang, ``Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing," in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2003), pp. 851--854, Kitakyushu, Japan, January. 2003.
34. H.-C. Lee, Y.-W. Chang, J.-M. Hsu, and H. Yang, ``Multilevel floorplanning/placement for large-scale modules using B*-trees," in Proc. of ACM/IEEE Design Automation Conference (DAC-2003), pp. 812--817, Anaheim, CA, June 2003.
35. T.-Y. Ho, Y.-W. Chang, S.-J. Chen, and D. T. Lee, "A fast crosstalk- and performance-driven multilevel routing system," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2003), pp. 382--387, San Jose, Nov. 2003.
36. Y.-H. Cheng and Y.-W. Chang, ``Integrating buffer planning with floorplanning for simultaneous multi-objective Optimization," in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2004), pp. 624--627, Yokohama, Japan, January 2004.
37. S.-W. Tu, J.-Y. Jou, and Y.-W. Chang, "Layout techniques for for on-chip interconnect inductance reduction," in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2004), pp. 269-273, Yokohama, Japan, January 2004.
38. P.-H. Yu, C.-L.Yang, Y.-W. Chang, and H.-L. Chen, "Temporal floorplanning using 3D-subTCG," in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2004), pp. 725--730, Yokohama, Japan, January 2004. (Best Paper Nominee)
39. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, "Multilevel routing with antenna avoidance," in Proceedings of ACM International Symposium on Physical Design (ISPD-2004), pp. 34--40, Phoenix, Arizona, April 2004.
40. S.-W. Tu, J.-Y. Jou, and Y.-W. Chang, "RLC effects on worst-case switching patterns for on-chip buses," in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS-2004), Vol. 2, pp. 945--948, Vancouver, Canada, May 2004.
41. S.-W. Wu and Y.-W. Chang, ``Efficient power/ground network analysis for power integrity driven design methodology," in Proc. of ACM/IEEE Design Automation Conference (DAC-2004), pp. 177--180, San Diego, CA, June 2004.
42. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, "Multilevel routing with jumper insertion for antenna avoidance," in Proceedings of IEEE International SOC Conference (SOC-2004), pp. 63--66, Santa Clara, California, September 2004.
43. M.-C. Wu and Y.-W. Chang, "Placement with Alignment and Performance Constraints Using the B*-tree representation," in Proceedings of IEEE International Conference on Computer Design (ICCD-2004), pp. 568--571, San Jose, CA, September 2004.
44. P.-H. Yu, C.-L.Yang and Y.-W. Chang, "Temporal floorplanning using the T-tree formulation," in Proceedings of IEEE/ACM International Conference on computer-Aided Design (ICCAD-2004), pp. 300--305, San Jose, CA, November 2004.
45. J.-M. Hsu and Y.-W. Chang, "A reusable methodology for non-slicing floorplanning," in Proceedings of IEEE Asia and Pacific Conference on Circuits and Systems (APCCAS-2004), Tainan, Taiwan, December 2004.
46. T.-C. Chen and Y.-W. Chang, "Multilevel gridless routing considering optical proximity effects," in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2005), pp. 1160--1163, Shanghai, China, January 2005.
47. J.-Y. Wuu, T.-C. Chen, and Y.-W. Chang, "SoC test scheduling using the B*-tree based flooprlanning technique," in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2005), pp. 1188--1191, Shanghai, China, January 2005.
48. G.-M. Wu, J.-M. Lin, Y.-W. Chang, and R.-H. Chuang, "Placement with symmetry constraints for analog layout design," in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2005), pp. 1135--1138, Shanghai, China, January 2005.
49. T.-C. Chen and Y.-W. Chang, "Modern floorplanning based on fast simulated annealing," in Proceedings of ACM International Symposium on Physical Design (ISPD-2005), pp. 104--112, San Francisco, CA, April 2005.
50. T.-C. Chen, T.-C. Hsu, Z.-W. Jiang, and Y.-W. Chang, "NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs," in Proceedings of ACM International Symposium on Physical Design (ISPD-2005), pp. 236--238, San Francisco, CA, April 2005.
51. S.-M Lee, C.-W. Lee, Y.-W. Chang, C.-C. Su, and J.-Y. Chen, "Multilevel full-chip routing with testability and yield enhancement," in Proceedings of ACM International Workshop on System Level Interconnect Prediction (SLIP-2005), pp. 29--36, San Francisco, CA, April 2005.
52. S.-L. Wang and Y.-W. Chang, "Delay modelling for buffered RLC/RLY trees," in Proceedings of The 1st IEEE-TSA VLSI Design Automation and Test Conference (VLSI-DAT-2005), Hsinchu, Taiwan, April 2005.
53. S.-W. Tu, J.-Y. Jou, and Y.-W. Chang, "RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction," in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS-2005), pp. 4134--4137, Kobe, Japan, May 2005.
54. B.-Y. Su and Y.-W. Chang, ``An optimal jumper insertion algorithm for antenna effect avoidance/fixing ," in Proc. of ACM/IEEE Design Automation Conference (DAC-2005), pp. 325--328, Anaheim, CA, June 2005.
55. T.-Y. Ho, C.-F. Chang, Y.-W. Chang, and S.-J. Chen, ``Multilevel full-chip routing for the X-based architecture," in Proc. of ACM/IEEE Design Automation Conference (DAC-2005), pp. 597--602, Anaheim, CA, June 2005. (Best Paper Nominee)
56. Y.-W. Wu, P.-H. Yuh, C.-L. Yang, and Y.-W. Chang, "Joint exploration of architectural and physical design spaces with thermal consideration," in Proceedings of IEEE/ACM International Symposium on Low Power Electronic Design (ISLPED-05), pp. 123--126, August 2005.
57. C.-S. Shih, C.-L. Yang, M.-K. Ku, T.-W. Kuo, S.-Y. Chien, Y.-W. Chang, L.-G. Chen, "Reconfigurable Platform for Content Science Research," in Proceedings of the 11th IEEE International Conference on RTCSA, pp. 481--488, Hong Kong, China, 2005.
58. T.-C. Chen, Y.-W. Chang, and C.-C. Lin, "IMF: Interconnect-driven multilevel floorplanning for large-scale building-module designs," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2005), pp. 159--164, San Jose, Nov. 2005.
59. J.-W. Fang, I.-J. Lin, P.-H. Yuh, Y.-W. Chang, and J.-H. Wang, "A routing algorithm for flip chip design," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2005), pp. 753--758, San Jose, Nov. 2005.
60. C.-Y. Peng, W.-C. Chao, Y.-W. Chang, and J.-H. Wang, "Simultaneous block and I/O buffer floorplanning for flip-chip design," in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2006), pp. 213--218, Yokohama, Japan, January 2006.
61. K. S.-M. Li, Y.-W. Chang, C.-C. Su, C.-L. Lee, and J. E. Chen, "P1500 based interconnect diagnosis for delay and crosstalk faults" in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2006), pp. 366--371, Yokohama, Japan, January 2006.
62. T.-C. Chen, Y.-W. Chang, and S.-C. Lin, "A novel framework for multilevel full-chip gridless routing," in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2006), pp. 636--641, Yokohama, Japan, January 2006.
63. C.-W. Liu and Y.-W. Chang, "Floorplan and power/ground network co-synthesis for fast design convergence," to appear in Proceedings of ACM International Symposium on Physical Design (ISPD-2006), San Jose, CA, April 2006.
64. B.-Y. Su, Y.-W. Chang, and J. Hu, ``An optimal jumper insertion algorithm for antenna effect avoidance/fixing on general routing trees with obstacles," to appear in Proceedings of ACM International Symposium on Physical Design (ISPD-2006), San Jose, CA, April 2006.
65. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, "NTUplace2: a hybrid placer using partitioning and analytical techniques," in Proceedings of ACM/IEEE International Symposium on Physical Design (ISPD-2006), pp. 215--217, San Jose, CA, April 2006. (Won the 3rd place in the placement contest; #1 in wirelength cost, #2 in overall quality [less than 1% away from the #1], #3 in overall combined cost, quality + CPU time [less than 2% away from the #1])
66. Y.-W. Lin and Y.-W. Chang, "Thermal-driven interconnect optimization by gate and wire sizing," in Proceedings of The 2nd IEEE-TSA VLSI Design Automation and Test Conference (VLSI-DAT-2006), pp. 151--154, Hsinchu, Taiwan, April 2006.
67. C.-Y. Lai, S.-K. Jeng, Y.-W. Chang, and C.-C. Tsai, "Surface integral inductance extraction for general interconnect structures," in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS-2006), Kos, Greece, May 2006.
68. H.-Y. Chen, M.-F. Chiang, Y.-W. Chang, L. Chen, and B. Han, "Novel full-chip gridless routing considering double-via insertion," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2006), pp. 755--760, San Francisco, CA, July 2006.
69. P-H. Yuh, C.-L. Yang, and Y.-W. Chang, "Placement of digital microfluidic biochips using the T-tree formulation," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2006), pp. 931--934, San Francisco, CA, July 2006.
70. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, "A high quality analytical placer considering preplaced blocks and density constraint," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2006), pp. 187--192, San Jose, Nov. 2006. (Received the highest score in the partitioning/floorplanning/placement track)
71. W.-P. Lee, H.-Y. Liu, and Y.-W. Chang, "Voltage island aware floorplanning for power and timing optimization," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2006), pp. 389--394, San Jose, Nov. 2006.
72. H.-Y. Liu, C.-W. Lin, S.-J. Chou, W.-T. Tu, Y.-W. Chang, and S.-Y. Kuo, "Current path analysis for electrostatic discharge protection," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2006), pp. 510--515, San Jose, Nov. 2006.
73. Z.-W. Jiang and Y.-W. Chang, "An optimal simultaneous diode/jumper insertion algorithm for antenna fixing," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2006), pp. 669--674, San Jose, Nov. 2006.
74. C.-W. Lin, M.-C. Tsai, K.-Y. Lee, T.-C. Chen, T.-C. Wang, and Y.-W. Chang, "Recent research and emerging challenges in physical design for manufacturability/reliability," in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2007), pp. 238--243, Yokohama, Japan, January 2007. (invited paper)
75. I.-J. Lin, T.-Y. Lin, and Y.-W. Chang, ``Statistical circuit optimization considering device and interconnect process variations," to appear in Proceedings of ACM International Workshop on System Level Interconnect Prediction (SLIP-2007), Austin, TX, March 2007.
76. T.-C. Chen, Y.-L. Chuang, and Y.-W. Chang, "X-architecture placement based on effective wire models," in Proceedings of ACM International Symposium on Physical Design (ISPD-2007), pp. 87--94, Austin, TX, March 2007. (Best Paper Nominee; received the highest score)
77. C.-W. Lin, S.-Y. Chen, C.-F. Li, Y.-W. Chang, and C.-L. Yang, ``Efficient obstacle-avoiding rectilinear Steiner tree construction," in Proceedings of ACM International Symposium on Physical Design (ISPD-2007), pp. 127--134, Austin, TX, March 2007. (Best Paper Nominee)
78. Z.-W. Jiang, H.-C. Chen, T.-C. Chen, and Y.-W. Chang, "Challenges and solutions in modern VLSI placement," in Proceedings of The 3rd IEEE-TSA VLSI Design Automation and Test Conference (VLSI-DAT-2007), pp. 111--115, Hsinchu, Taiwan, April 2007. (invited paper)
79. J.-W. Fang, C.-H. Hsu, and Y.-W. Chang, "An integer linear programming algorithm for flip-chip routing," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2007), San Diego, CA, June 2007. (Best Paper Nominee; received the highest score in the beyond-die track)
80. T.-C. Chen, P.-H. Yuh, Y.-W. Chang, F.-J. Liu, and D. Liu, "MP-trees: a packing-based macro placement algorithm for mixed-size designs," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2007), San Diego, CA, June 2007. (received the 2nd highest score out of 52 papers in the physical design and manufacturability track)
81. H.-Y. Liu, W.-P. Lee, and Y.-W. Chang, "A provably good approximation algorithm for power optimization using multiple supply voltages," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2007), San Diego, CA, June 2007.
82. C.-F. Li, P.-H. Yuh, C.-L. Yang, and Y.-W. Chang, "Post-placement leakage optimization for partially dynamically reconfigurable FPGAs," in Proceedings of IEEE/ACM International Symposium on Low Power Electronic Design (ISLPED-07), August 2007.
83. W.-P. Lee, H.-Y. Liu, and Y.-W. Chang, "An ILP algorithm for post-floorplanning voltage-island generation, in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007.
84. Y.-P. Chen, J.-W. Fang, and Y.-W. Chang, "ECO timing optimization using spare cells, in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007.
85. I.-J. Lin and Y.-W. Chang, "An efficient algorithm for statistical circuit optimization using Lagrangian relaxation, in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007.
86. C.-W. Lin. S.-L. Huang, K.-C. Hsu, M.-X. Lee, and Y.-W. Chang, "Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction, in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007.
87. H.-Y. Chen, S.-J. Chou, S.-L. Wang, and Y.-W. Chang, "Novel wire density driven full-chip routing for CMP variation control, in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007. (Best Paper Nominee)
88. P.-H. Yu, C.-L. Yang, and Y.-W. Chang, "BioRoute: A network flow based routing algorithm for digital microfluidic biochips, in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007.
89. T.-C. Chen, M. Cho, D. Z. Pan and Y.-W. Chang, "Metal-density driven placement for CMP variation and routability," in Proceedings of ACM International Symposium on Physical Design (ISPD-2008), Portland, Oregon, April 2008.
90. W.-P. Lee, H.-Y. Liu, K.-H. Ho, and Y.-W. Chang, "Sensitivity-based multiple-Vt cell swapping for leakage power reduction under timing requirements," in Proceedings of The 4th IEEE-TSA VLSI Design Automation and Test Conference (VLSI-DAT-2008), Hsinchu, Taiwan, April 2008.
91. T.-C. Chen, G.-W. Liao, and Y.-W. Chang, "Predictive formulae for OPC with applications to lithography-friendly routing," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2008), Anaheim, CA, June 2008. (Best Paper Nominee; received the highest score in the Physical Design & Manufacturability track)
92. Z.-W. Jiang, B.-Y. Su, and Y.-W. Chang, "Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2008), Anaheim, CA, June 2008.
93. P.-H. Yuh, S. Sapatnekar, C.-L. Yang, and Y.-W. Chang, "A progressive-ILP based routing algorithm for cross-referencing biochips," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2008), Anaheim, CA, June 2008.
94. J.-W. Fang and Y.-W. Chang, "Area-I/O flip-chip routing for chip-package co-design," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2008), San Jose, Nov. 2008.
95. J.-W. Fang, K.-H. Ho, and Y.-W. Chang, "Placement and routing for chip-package-board co-design considering differential pairs," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2008), San Jose, Nov. 2008.
96. C.-H. Hsu, H.-Y. Chen, and Y.-W. Chang, "Multi-layer global routing considering via and wire capacities," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2008), San Jose, Nov. 2008.
97. H.-C. Chen, Y.-L. Chuang, Y.-W. Chang, and Y.-C. Chang, "Constraint graph-based macro placement for mixed-size circuit designs," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2008), San Jose, Nov. 2008.
98. C.-H. Hsu, H.-Y. Chen, and Y.-W. Chang, " High-performance global routing with fast overflow reduction," in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2009), Yokohama, Japan, January 2009.
99. H. Graeb, F. Balasa, R. Castro-Lopez, Y.-W. Chang, F. Fernandez, P.-H. Lin, M. Strasser, "Analog Layout Synthesis - Recent Approaches," in Proceedings of ACM/IEEE Design Automation and Test in Europe (DATE-2009), Niece, France, March 2009.
100. W.-P. Lee, D. Marculescu, and Y.-W. Chang, "Post-Floorplanning Power/Ground Ring Synthesis for Multiple-Supply-Voltage Designs," in Proceedings of ACM International Symposium on Physical Design (ISPD-2009), San Diego, CA, April 2009.
101. C.-Y. Lin and Y.-W. Chang, "ILP-based pin-count aware design methodology for microfluidic biochips," to appear in Proceedings of ACM/IEEE Design Automation Conference (DAC-2009), San Francisco, CA, July 2009.
102. P.-H. Lin, H. Zhang, D. F. Wong, and Y.-W. Chang, "Thermal-driven analog placement considering device matching ," to appear in Proceedings of ACM/IEEE Design Automation Conference (DAC-2009), San Francisco, CA, July 2009.
103. Z.-W. Jiang, M-K. Hsu, Y.-W. Chang, and K.-Y. Chao, "Spare-cell-aware multilevel analytical placement," to appear in Proceedings of ACM/IEEE Design Automation Conference (DAC-2009), San Francisco, CA, July 2009.
104. J.-W. Fang, D. F. Wong, and Y.-W. Chang, "Flip-chip routing with unified area-I/O pad assignments for package-board co-design," to appear in Proceedings of ACM/IEEE Design Automation Conference (DAC-2009), San Francisco, CA, July 2009.
105. Y.-L. Chuang, P.-W. Lee, and Y.-W. Chang, "Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs," to appear in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2009), San Jose, Nov. 2009. (Best Paper Nominee)
106. P.-W. Lee, C.-W. Lin, Y.-W. Chang, "An efficient pre-assignment routing algorithm for flip-chip designs," to appear in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2009), San Jose, Nov. 2009.
107. C.-H. Hsu, Y.-W. Chang, S. R. Nassif, "Simultaneous layout migration and decomposition for double patterning technology," to appear in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2009), San Jose, Nov. 2009.
108. T.-F. Chien, W.-C. Chao, Chien-Mo Li, K.-Y. Liao, Y.-W. Chang, M.-T. Chang, M.-H. Tsai, and C.-M. Tseng, " BIST design optimization for large-scale embedded memory cores," to appear in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2009), San Jose, Nov. 2009.
109. X.-W. Shih, C.-C. Cheng, Y.-K. Ho, and Y.-W. Chang, "Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization," to appear in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2010), Taipei, Taiwan, January 2010.
110. K.-H. Ho, J.-H. Jiang, Y.-W. Chang, "TRECO: Dynamic technology remapping for timing engineering change orders," to appear in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2010), Taipei, Taiwan, January 2010.
111. P. Falkenstern, Y. Xie, Y. Wang, and Y.-W. Chang, " Three-dimensional integrated circuit (3D IC) floorplan and power/ground network co-synthesis," to appear in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2010), Taipei, Taiwan, January 2010.
112. H.-Y. Chen, S.-J. Chou, and Y.-W. Chang, "Density gradient minimization with coupling-constrained dummy fill for CMP control," to appear in Proceedings of ACM International Symposium on Physical Design (ISPD-2010), San Diego, CA, March 2010.
Other Conference Papers/Reports:
1. Y.-D. Chang, G.-M. Wu, and Y.-W. Chang, "Can FPD switch matrices be universal?," The 8th VLSI Design/CAD Symposium, pp. 253-256, Nangtou, Taiwan, Aug. 1997.
2. Y.-D. Chang, Y.-W. Chang, and M. Shyu, "Design and analysis of universal switch modules for hierarchical FPGAs," in Proceedings of the 9th VLSI Design/CAD Symposium, Nangtou, Taiwan, Aug. 1998.
3. Y.-W. Chang and J.-M. Lin, "Channel segmentation design for FPGAs," in Proceedings of the 9th VLSI Design/CAD Symposium, Nangtou, Taiwan, Aug. 1998.
4. J.-M. Lin, S.-R. Pan, and Y.-W. Chang, ``A timing-driven matching-based algorithm for array-based FPGA routing," in Proceedings of the 10th VLSI Design/CAD Symposium, Nangtou, Taiwan, Aug. 1999.
5. H.-R. Jiang, S.-R. Pan, Y.-W. Chang, and J.-Y. Jou, ``Reliable crosstalk-driven interconnect optimization in the deep submicron technology," in Proceedings of the 10th VLSI Design/CAD Symposium, Nangtou, Taiwan, Aug. 1999. (Received the 2nd highest score out of the 101 papers and the highest score in the CAD track; score = 3.67 based on 4.0.)
6. G.-M. Wu, J.-M. Lin, M. C.-T. Chao, and Y.-W. Chang, ``Generic ILP-based approaches for time-multiplexed FPGA partitioning," in Proceedings of The 11th VLSI Design/CAD Symposium, Pingdong, Taiwan, Aug. 2000.
7. G.-M. Wu and Y.-W. Chang, ``Precedence-constrained placement for dynamically reconfigurable FPGAs," in Proceedings of The 11th VLSI Design/CAD Symposium, Pingdong, Taiwan, Aug. 2000.
8. S.-R. Pan and Y.-W. Chang, ``Performance optimization by wire/buffer sizing under the transmission line model," in Proceedings of The 11th VLSI Design/CAD Symposium, Pingdong, Taiwan, Aug. 2000.
9. C.-Y. Chang, Y.-W. Chang, and I. H.-R. Jiang, ``Simultaneous buffer-insertion/-sizing and wire-sizing formulae with applications to interconnect-driven floorplanning," in Proceedings of The 11th VLSI Design/CAD Symposium, Pingdong, Taiwan, Aug. 2000. (Received Best Student Paper Award; two out of 125 papers were selected.)
10. S.-M. Li, Y.-H. Cherng, and Y.-W. Chang, ``Buffer insertion for noise-aware interconnect-driven floorplanning," in Proceedings of The 12th VLSI Design/CAD Symposium, Hsinchu, Taiwan, Aug. 2001.
11. J.-M. Lin, S.-P. Lin, and Y.-W. Chang, ``A P-admissible non-slicing floorplan representation with a worst-case linear-time packing scheme," in Proceedings of The 12th VLSI Design/CAD Symposium, Hsinchu, Taiwan, Aug. 2001. (Received the highest score out of 152 papers.)
12. S.-C. Lee, J.-M. Hsu, and Y.-W. Chang, ``Multilevel large-scale module placement/floorplanning using B*-trees," in Proceedings of The 12th VLSI Design/CAD Symposium, Hsinchu, Taiwan, Aug. 2001.
13. S.-W. Tu, W.-Z. Shen, Y.-W. Chang, and T.-C. Chen, ``Inductance modeling for on-chip interconnects," in Proceedings of The 12th VLSI Design/CAD Symposium, Hsinchu, Taiwan, Aug. 2001.
14. Y.-H. Cheng, Y.-W. Chang and R.-H. Chuang, ``Integrating Buffer Planning with Floorplanning for Simultaneous Area, Timing, Noise, and Congestion Optimization," in Proceedings of The 13th VLSI Design/CAD Symposium, Taitung, Taiwan, Aug. 2002. (Received the highest score out of 182 papers; score = 4.0 based on 4.0.)
15. S.-P. Lin and Y.-W. Chang, ``A performance-driven multilevel router," in Proceedings of The 13th VLSI Design/CAD Symposium, Taitung, Taiwan, Aug. 2002. (Received the 2nd highest score out of 182 papers; score = 3.5 based on 4.0.)
16. H.-E. Yi, Y.-W. Chang, and M.-C. Wu, ``A B*-tree Based Placer for Boundary Modules," in Proceedings of The 13th VLSI Design/CAD Symposium, Taitung, Taiwan, Aug. 2002.
17. Y.-W. Chang, L.-G. Chen, C.-W. Jen, and M.-C. Lan, ``The VLSI Circuits and Systems Education Program in Taiwan," to appear in Proceedings of 2003 International Conference on Engineering Education, Valencia, Spain, July 2003.
18. S.-W. Tu, J.-Y. Jou, and Y.-W. Chang, "Layout Techniques for Minimizing On-Chip Interconnect Inductance," The 14th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2003.
19. M.-C. Wu and Y.-W. Chang, "Placement with an Optimal Evaluation Scheme for Alignment and Performance Constraints Using B*-trees," The 14th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2003.
20. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, "A fast crosstalk-driven multilevel routing system," The 14th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2003.
21. S.-L. Wang and Y.-W. Chang, "Accurate Delay Formulae for Buffered RLC Trees," The 14th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2003.
22. T.-C. Chen and Y.-W. Chang, "Multilevel gridless routing," The 15th VLSI Design/CAD Symposium, Pin-Tung, Taiwan, Aug. 2004.
23. S.-W. Tu, Y.-W. Chang, and J.-Y. Jou, "RLC circuit simulation and bus encoding for delay reduction," The 15th VLSI Design/CAD Symposium, Pin-Tung, Taiwan, Aug. 2004.
24. T.-C. Chen and Y.-W. Chang, "Fixed-outline floorplanning using the B*-tree representation," The 15th VLSI Design/CAD Symposium, Pin-Tung, Taiwan, Aug. 2004.
25. C.-Y. Lai, S.-K. Jeng, and Y.-W. Chang, "Surface integral inductance extraction for general interconnect structures," The 15th VLSI Design/CAD Symposium, Pin-Tung, Taiwan, Aug. 2004.
26. T.-C. Chen and Y.-W. Chang, "Full-chip gridless routing using a novel multilevel framework," The 16th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2005.
27. K. S.-M. Li, C.-L. Lee, Y.-W. Chang, C.-C. Su, and J. E. Chen, "Multilevel full-chip routing with testability and yield enhancement," The 16th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2005.
28. J.-W. Fang, I.-J. Lin, and Y.-W. Chang, "An RDL router for flip-chip design," The 16th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2005.
29. C.-F. Chang, T.-Y. Ho, and Y.-W. Chang, "XRoute: a multilevel routing system for the X-based architecture," The 16th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2005.
30. T.-C. Chen and Y.-W. Chang, "A new multilevel framework for large-scale interconnect-driven floorplanning," The 16th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2005.
31. K. S.-M. Li, C.-L. Lee, Y.-W. Chang, C.-C. Su, and J. E. Chen, "P1500 based interconnect delay and crosstalk fault diagnosis," The 16th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2005.
32. T.-C. Chen, P.-H. Yuh, Y.-W. Chang, F.-J. Huang, and D. Liu, "A Macro Placer Based on a New Packing Representation," The 17th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2006.
33. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, "A Novel Analytical Mixed-Size Placement Algorithm Considering Preplaced Blocks," The 17th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2006.
34. W.-P. Lee, H.-Y. Liu, and Y.-W. Chang, "Timing-Constrained Voltage Island Assignment and Floorplanning for Power Optimization," The 17th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2006.
35. T.-Y. Ling, I-J. Lin, and Y.-W. Chang, "A Statistical Circuit Optimization Algorithm under Thermal and Timing Constraints," The 17th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2006.
36. S.-J. Chou, C.-H. Hsu, J.-H. Jiang, and Y.-W. Chang, "Statistical Timing-Yield Optimization via Latch Substitution," The 17th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2006.
37. P.-H. Yuh, C.-L. Yang, and Y.-W. Chang, "BioRoute: A network-flow based routing algorithm for digital microfluidic biochips," The 18th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2007. (Best Paper Award; Received the highest score in the EDA category; the first year awarding best papers after 2000)
38. T.-C. Chen, G.-W. Liao, and Y.-W. Chang, "Lithography-aware routing with predictive OPC formulae," The 18th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2007.
39. H.-C. Chen, Y.-L. Chuang, and Y.-W. Chang, "A high quality transitive-closure-graph-based macro placer," The 18th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2007.
40. C.-H. Hsu, H.-Y. Chen, and Y.-W. Chang, "Fast global routing with forbidden-region rerouting," The 19th VLSI Design/CAD Symposium, Ping-Tong, Taiwan, Aug. 2008.
41. C.-H. Hsu, H.-Y. Chen, and Y.-W. Chang, "Global routing with via/wire capacity considerations," The 19th VLSI Design/CAD Symposium, Ping-Tong, Taiwan, Aug. 2008.
42. H.-Y. Chen, S.-J. Chou, and Y.-W. Chang, "Coupling-constrained dummy fill for density gradient minimization," The 19th VLSI Design/CAD Symposium, Ping-Tong, Taiwan, Aug. 2008. (Best Paper Award)
43. P.-W. Lee, C.-W. Lin, and Y.-W. Chang, "Fast pre-assignment flip-chip routing," The 20th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2009. (Best Paper Nominee; best paper award selection was cancelled due to typhoon Morakot)
44. X.-W. Shih, C.-C. Cheng, Y.-K. Ho, and Y.-W. Chang, "NTUclock: A high-quality blockage-avoiding buffered clock-tree router for modern circuit designs," The 20th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2009.
45. T.-F. Chien, W.-C. Chao, Chien-Mo Li, K.-Y. Liao, Y.-W. Chang, M.-T. Chang, M.-H. Tsai, and C.-M. Tseng, "SoC memory BIST design optimization," The 20th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2009.
46. K.-H. Ho, J.-H. Jiang, and Y.-W. Chang, "Technology remapping for ECO timing optimization," The 20th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2009.
Technical Reports:
1. Y.-W. Chang, D. F. Wong, and C. K. Wong, ``Universal switch modules for FPGA design,'' Dept. of Computer Sciences, University of Texas at Austin, TR95-27, August 1995.
2. Y.-W. Chang, K. Zhu, D. F. Wong, and C. K. Wong, ``Analysis of FPGA/FPIC switch modules,'' Dept. of Computer Sciences, University of Texas at Austin, TR96-32, September 1996.
3. Y.-W. Chang, H.-R. Jiang, and J.-Y. Jou, ``Lagrangian relaxation for post-layout optimization for SoC design,'' Engineering Science & Technology Bulletin, National Science Council, pp. 130-133, September 2001.
Dissertation:
Other Articles:
1. Y.-W. Chang, "Ansel Adams--Master of the Straight Photography (in Chinese)," Light & Shadows, No. 6, June 1985.
2. Y.-W. Chang, "Introduction to photography (in Chinese)," Light & Shadows, No. 13, April 1987.
3. Y.-W. Chang, "Thoughts on the meanings of images (in Chinese)," Light & Shadows, No. 17, May 1988.